Ing.

Josef Strnadel

Ph.D.

FIT, UPSY – odborný asistent

+420 54114 1211
strnadel@fit.vutbr.cz

Odeslat VUT zprávu

Ing. Josef Strnadel, Ph.D.

Publikace

  • 2020

    STRNADEL, J. Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. In Design, Automation & Test in Europe Conference & Exhibition (DATE). Grenoble: IEEE Computer Society, 2020. s. 1-4.
    Detail | WWW

  • 2019

    STRNADEL, J. Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. In Design, Automation & Test in Europe Conference & Exhibition (DATE). Florence: IEEE Computer Society, 2019. s. 614-617. ISBN: 978-3-9819263-2-3.
    Detail | WWW

  • 2018

    STRNADEL, J. Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. In Proceedings of 8th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA). Lecture Notes in Computer Science. Lecture Notes in Computer Science, Vol. 11245. Cham: Springer International Publishing, 2018. s. 414-429. ISSN: 0302-9743.
    Detail | WWW

    STRNADEL, J. Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Design and Test, 2018, roč. 35, č. 2, s. 57-63. ISSN: 2168-2356.
    Detail | WWW

  • 2017

    STRNADEL, J. On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2017. s. 352-355. ISBN: 978-1-5386-2146-2.
    Detail | WWW

  • 2016

    STRNADEL, J. Souhrnná výzkumná zpráva k projektu Vývoj ovladače rekonfigurovatelné platformy pro FreeRTOS. Brno: RehiveTech, spol. s r.o., 2016. s. 1-2.
    Detail | WWW

    STRNADEL, J. Modeling and Analysis of Fault-Tolerant Systems by Means of UPPAAL SMC: Method and Benefits. In Informal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Bratislava: Slovak University of Technology in Bratislava, 2016. s. 32-37. ISBN: 978-80-8086-256-5.
    Detail | WWW

    STRNADEL, J. On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. In Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques. Lecture Notes in Computer Science. Lecture Notes in Computer Science, Vol. 9952. Cham: Springer International Publishing, 2016. s. 166-181. ISBN: 978-3-319-47166-2. ISSN: 0302-9743.
    Detail | WWW

    STRNADEL, J.; RIŠA, M. On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC. In Proceedings of the 24th Austrian Workshop on Microelectronics. Villach: IEEE Computer Society Press, 2016. s. 45-50. ISBN: 978-1-5090-1040-0.
    Detail | WWW

  • 2015

    STRNADEL, J. Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. In Proceedings of the 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems. Brno: Brno University of Technology, 2015. s. 39-44. ISBN: 978-1-4673-7967-0.
    Detail | WWW

    STRNADEL, J. Souhrnná výzkumná zpráva k projektu Vývoj ovladače rekonfigurovatelné platformy pro FreeRTOS. Brno: RehiveTech, spol. s r.o., 2015. s. 1-2.
    Detail | WWW

  • 2014

    STRNADEL, J.; CONTE, G. Producing Unique Identifiers and Random Numbers on Basis of Unclonable Parameters of Microcontrollers and Undesired Effects. In Proceedings of Electronic Devices and Systems IMAPS CS International Conference 2014. Brno: Brno University of Technology, 2014. s. 82-87. ISBN: 978-80-214-4985-5.
    Detail | WWW

    STRNADEL, J.; POKORNÝ, M. Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. In Proceedings of the 2014 17th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2014. s. 333-340. ISBN: 978-1-4799-5793-4.
    Detail | WWW

    STRNADEL, J.; SLIMAŘÍK, F. Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Computing and Informatics, 2014, roč. 33, č. 4, s. 757-782. ISSN: 1335-9150.
    Detail | WWW

    STRNADEL, J. Souhrnná výzkumná zpráva k projektu Vývoj ovladače rekonfigurovatelné platformy pro FreeRTOS. Brno: RehiveTech, spol. s r.o., 2014. s. 1-2.
    Detail | WWW

  • 2013

    STRNADEL, J. Plánování úloh v systémech RT - IV: víceprocesorové prostředí. Automa, 2013, roč. 19, č. 1, s. 44-46. ISSN: 1210-9592.
    Detail | WWW

    STRNADEL, J. Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. In Architecture of Computing Systems - ARCS 2013. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 7767. Berlin: Springer Verlag, 2013. s. 98-109. ISBN: 978-3-642-36423-5. ISSN: 0302-9743.
    Detail | WWW

    STRNADEL, J. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. In Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013. s. 24-29. ISBN: 978-1-4673-6133-0.
    Detail | WWW

    STRNADEL, J. Plánování úloh v systémech RT - V: zvyšování provozuschopnosti systémů. Automa, 2013, roč. 19, č. 2, s. 46-49. ISSN: 1210-9592.
    Detail | WWW

  • 2012

    STRNADEL, J. Plánování úloh v systémech RT - III: přetížení systému. Automa, 2012, roč. 18, č. 12, s. 44-47. ISSN: 1210-9592.
    Detail | WWW

    STRNADEL, J. Plánování úloh v systémech RT - I: závislé úlohy. Automa, 2012, roč. 18, č. 10, s. 42-45. ISSN: 1210-9592.
    Detail | WWW

    STRNADEL, J. Plánování úloh v systémech RT - II: neperiodické úlohy. Automa, 2012, roč. 18, č. 11, s. 44-46. ISSN: 1210-9592.
    Detail | WWW

    STRNADEL, J.; SLIMAŘÍK, F. On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. In Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Pistacaway: IEEE Computer Society, 2012. s. 272-279. ISBN: 978-0-7695-4798-5.
    Detail | WWW

    STRNADEL, J. Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems. In Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). Tallin: IEEE Computer Society, 2012. s. 121-126. ISBN: 978-1-4673-1188-5.
    Detail | WWW

    STRNADEL, J.; RAJNOHA, P. Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study. Acta Electrotechnica et Informatica, 2012, roč. 12, č. 4, s. 17-29. ISSN: 1335-8243.
    Detail | WWW

  • 2011

    STRNADEL, J. Návrh časově kritických systémů IV: realizace prostředky RTOS. Automa, 2011, roč. 2011, č. 4, s. 58-60. ISSN: 1210-9592.
    Detail | WWW

    RUMPLÍK, M.; STRNADEL, J. On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. In Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011. Oulu: IEEE Computer Society, 2011. s. 367-374. ISBN: 978-0-7695-4494-6.
    Detail | WWW

    STRNADEL, J. Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads. In Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design. Oulu: Johannes Kepler University Linz, 2011. s. 21-22. ISBN: 978-3-902457-30-1.
    Detail | WWW

    STRNADEL, J. Návrh časově kritických systémů III: priorita úloh. Automa, 2011, roč. 2011, č. 2, s. 50-52. ISSN: 1210-9592.
    Detail | WWW

  • 2010

    STRNADEL, J. Návrh časově kritických systémů II: úlohy reálného času. Automa, 2010, roč. 2010, č. 12, s. 18-19. ISSN: 1210-9592.
    Detail | WWW

    STRNADEL, J. Návrh časově kritických systémů I: specifikace a verifikace. Automa, 2010, roč. 2010, č. 10, s. 42-44. ISSN: 1210-9592.
    Detail | WWW

    KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. s. 364-369. ISBN: 978-1-4244-6610-8.
    Detail | WWW

    KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. In Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010. s. 644-651. ISBN: 978-0-7695-4171-6.
    Detail | WWW

    STRNADEL, J. Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel. In Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010. Zlín: Tomas Bata University in Zlín, 2010. s. 99-104. ISBN: 978-80-7318-940-2.
    Detail | WWW

    ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274. Berlin: Springer Verlag, 2010. s. 181-192. ISBN: 978-3-642-15322-8. ISSN: 0302-9743.
    Detail | WWW

    ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. 142 s. ISBN: 978-80-214-4209-2.
    Detail

  • 2009

    STRNADEL, J. Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems. In Proceedings of 32th International Conference TD - DIAGON 2009. Zlín: Tomas Bata University in Zlín, 2009. s. 19-24. ISBN: 978-80-7318-840-5.
    Detail | WWW

    STRNADEL, J.; RŮŽIČKA, R. Testability Analysis Driven Data Path Modification And Controller Synthesis. In Proceedings of 16th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2009. s. 363-368. ISBN: 978-80-214-3933-7.
    Detail | WWW

  • 2008

    STRNADEL, J. Testability Enhancement of Multilevel Designs Guided by Testability Analysis Method. In Proceedings of Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2008. s. 367-372. ISBN: 978-80-214-3717-3.
    Detail | WWW

    STRNADEL, J.; PEČENKA, T.; KOTÁSEK, Z. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, 2008, roč. 27, č. 6, s. 913-930. ISSN: 1335-9150.
    Detail | WWW

    STRNADEL, J. Analýza a zlepšení testovatelnosti číslicových obvodů na úrovni meziregistrových přenosů. Brno: Fakulta informačních technologií VUT v Brně, 2008. 187 s. ISBN: 978-80-214-3599-5.
    Detail | WWW

    STRNADEL, J. TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. In Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008. s. 865-872. ISBN: 978-0-7695-3277-6.
    Detail | WWW

  • 2007

    RŮŽIČKA, R.; STRNADEL, J. Test Controller Synthesis Constrained by Circuit Testability Analysis. In Proceedings of 10th Euromicro Conference on Digital System Design, Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society Press, 2007. s. 626-633. ISBN: 0-7695-2978- X.
    Detail

    STRNADEL, J. On Encoding and Utilization of Diagnostic Information Extracted from Design- Data for Testability Analysis Purposes. In Proceedings of the 6th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2007. s. 171-176. ISBN: 978-80-227-2697- 9.
    Detail

    STRNADEL, J. Educational Toolset for Experimenting with Optimizations in the Area of Cost/Quality Trade- Offs Related to Digital Circuit Diagnosis. In Proceedings of 14th Electronic Devices and Systems IMAPS CS International Conference. Brno: Brno University of Technology, 2007. s. 333-338. ISBN: 978-80-214-3470- 7.
    Detail

  • 2006

    STRNADEL, J. On Distribution of Testability Values in Scan-Layout State- Space. In Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006. s. 308-313. ISBN: 80-8073-598- 0.
    Detail

    STRNADEL, J. Testability Analysis and Improvements of Register- Transfer Level Digital Circuits. Computing and Informatics, 2006, roč. 25, č. 5, s. 441-464. ISSN: 1335- 9150.
    Detail

    PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. In Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. s. 504-514. ISBN: 0-7695-2609- 8.
    Detail

    STRNADEL, J.; DHALI, A. Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. In Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006. s. 360-367. ISBN: 0-7695-2546- 6.
    Detail

    KOTÁSEK, Z.; STRNADEL, J. SET: Interactive Tool for Learning and Training Scan- Based DFT Principles and Their Consequences to Parameters of Embedded System. In Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006. s. 497-498. ISBN: 0-7695-2546- 6.
    Detail

    STRNADEL, J. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State- Space. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. s. 161-162. ISBN: 1-4244-0184- 4.
    Detail

  • 2005

    PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In Proc. of the 2005 NASA/ DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. s. 51-58. ISBN: 0-7695-2399- 4.
    Detail | WWW

    KOTÁSEK, Z., STRNADEL, J. Testing Tools for Training and Education. In Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005. s. 671-676. ISBN: 83-919289-9- 3.
    Detail

    STRNADEL, J., KOTÁSEK, Z. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005. s. 420-427. ISBN: 0-7695-2433- 8.
    Detail

    STRNADEL, J. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. In Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. s. 190-193. ISBN: 963-9364-48-7.
    Detail

    KOTÁSEK, Z., STRNADEL, J., PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. s. 186-189. ISBN: 963-9364-48-7.
    Detail | WWW

    STRNADEL, J., PEČENKA, T., SEKANINA, L. On Testability Analysis Driven Generation of Synthetic Register- Transfer Level Benchmark Circuits. In Proceedings of 5th Electronic Circuits and Systems Conference. Bratislava: Slovak University of Technology in Bratislava, 2005. s. 107-110.
    Detail

  • 2004

    KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Registers in RTL Structures. In Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004. Technical Report TR-2004- 6. Nicosia: Department of Computer Science of University of Cyprus, 2004. s. 317-320. ISBN: 3-540- 41613.
    Detail

    STRNADEL, J., KOTÁSEK, Z. System ScanEduTool, didactic instrument for education of scan technique principles. Brno: Faculty of Information Technology BUT, 2004.

    STRNADEL, J. Analýza a zlepšení testovatelnosti číslicového obvodu na úrovni meziregistrových přenosů. In Zborník príspevkov Česko-slovenského seminára pre študentov doktorandského štúdia Počítačové architektúry & Diagnostika (PAD). Bratislava: Slovenská akademie věd, 2004. s. 138-143. ISBN: 80-969202-0- 0.
    Detail

    PEČENKA, T., KOTÁSEK, Z., STRNADEL, J. Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores. In Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. s. 99-104. ISBN: 80-969117-9- 1.
    Detail | WWW

    PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. In Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. s. 107-108. ISBN: 000000000.
    Detail | WWW

    KOTÁSEK, Z., PEČENKA, T., STRNADEL, J., MIKA, D., SEKANINA, L. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. s. 229-234. ISBN: 80-8073-150- 0.
    Detail | WWW

    STRNADEL, J. Analýza a zlepšení testovatelnosti číslicového obvodu na úrovni meziregistrových přenosů. Brno: 2004.
    Detail | WWW

  • 2003

    STRNADEL, J. Algebraic Analysis of Feedback Loop Dependencies in Order of Improving RTL Digital Circuit Testability. In Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznan: Publishing House of Poznan University of Technology, 2003. s. 303-304. ISBN: 83-7143-557- 6.
    Detail

    KOTÁSEK, Z., MIKA, D., STRNADEL, J. Test scheduling for embedded systems. In Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003. s. 463-467. ISBN: 0-7695-2003- 0.
    Detail

    STRNADEL, J. Nested Loops Degree Impact on RTL Digital Circuit Testability. In Programmable Devices and Systems. Oxford: Elsevier Science, 2003. s. 202-207. ISBN: 0-08-044130- 0.
    Detail | WWW

    STRNADEL, J. Analýza a zlepšení testovatelnosti RTL číslicového obvodu. In Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2003. s. 24-29. ISBN: 80-214-2471- 0.
    Detail

    KOTÁSEK, Z., MIKA, D., STRNADEL, J. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. In Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003. s. 233-238. ISBN: 83-7143-557- 6.
    Detail

    STRNADEL, J. Scan Layout Encoding by Means of a Binary String. In Proceedings of 37th International Conference on Modelling and Simulation of Systems. Ostrava: 2003. s. 115-122. ISBN: 80-85988-86- 0.
    Detail | WWW

  • 2002

    ZBOŘIL, F., KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Feedback Loops in RTL Structures. In Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. s. 142-147. ISBN: 80-7099-879- 2.
    Detail

    STRNADEL, J., KOTÁSEK, Z. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. In Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. s. 44-51. ISBN: 80-214-2094- 4.
    Detail | WWW

    STRNADEL, J., KOTÁSEK, Z. Normalized Testability Measures at RT Level: Utilization and Reasons for Creation. In Proceedings of 36th International Conference MOSIS` 02 Modeling and Simulation of Systems. Vol. I. Ostrava: 2002. s. 297-304. ISBN: 80-85988-71- 2.
    Detail | WWW

    STRNADEL, J. Evaluating Cost/Quality Trade- off Solutions Proposed During a DFT Process. In Proceeding of 8th Conference Student EEICT 2002. Brno: Brno University of Technology, 2002. s. 506-510. ISBN: 80-214-2116- 9.
    Detail

    STRNADEL, J., KOTÁSEK, Z. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. In Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD' 2002. Los Alamitos: IEEE Computer Society Press, 2002. s. 166-173. ISBN: 0-7695-1790- 0.
    Detail | WWW

    STRNADEL, J. Normalized Testability Measures Based on RTL Digital Circuit Graph Model Analysis. In Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. s. 200-205. ISBN: 80-7099-879- 2.
    Detail | WWW

    MIKA, D., KOTÁSEK, Z., STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. In Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. s. 135-141. ISBN: 80-7099-879- 2.
    Detail

  • 2001

    STRNADEL, J., KOTÁSEK, Z., RŮŽIČKA, R. Formal and Analytical Approaches to the Testability Analysis - the Comparison. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS Ltd., Hungary, 2001. s. 123-128. ISBN: 963-7175-16- 4.
    Detail

    KOTÁSEK, Z., STRNADEL, J., RŮŽIČKA, R., ZBOŘIL, F. Two Level Testability System. In Proceedings of the 35th Spring International Conference MOSIS' 01. Ostrava: 2001. s. 433-440. ISBN: 80-85988-57- 7.
    Detail

    HLAVIČKA, J., KOTÁSEK, Z., STRNADEL, J., RŮŽIČKA, R. Interactive Tool for Behavioral Level Testability Analysis. In Proceedings of the IEEE ETW 2001. Stockholm: 2001. s. 117-119.
    Detail

    STRNADEL, J., KOTÁSEK, Z. RTL Testability Analysis Based on Genetic Algorithm Implementation. In Proceedings of the Tenth ICNACSA. Plovdiv: unspecified agency, 2001. s. 89 ( s.)
    Detail

    KOTÁSEK, Z., STRNADEL, J. Analytic Approach to RTL Testability Analysis. In Proceedings of 7th Conference Student FEI 2001. Brno: Brno University of Technology, 2001. s. 363 ( s.)ISBN: 80-214-1860- 5.
    Detail

    STRNADEL, J., KOTÁSEK, Z. RTL Testability Analysis Based on Genetic Algorithm Implementation. In Proceedings of the IWCIT' 01. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB- TU Ostrava, 2001. s. 83-88. ISBN: 80-7078-907- 7.
    Detail

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