Detail publikace

On Distribution of Testability Values in Scan-Layout State-Space

STRNADEL, J.

Originální název

On Distribution of Testability Values in Scan-Layout State-Space

Anglický název

On Distribution of Testability Values in Scan-Layout State-Space

Jazyk

en

Originální abstrakt

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout, the better testability properties correspond to the scan-layout.

Anglický abstrakt

In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greater number of multiple scan-chains within particular scan-layout, the better testability properties correspond to the scan-layout.

Dokumenty

BibTex 


@inproceedings{BUT22271,
  author="Josef {Strnadel}",
  title="On Distribution of Testability Values in Scan-Layout State-Space",
  annote="In the paper, it is shown how are testability values distributed within the
scan-layout state-space for particular digital circuit. The goal of the paper was
to approve or dismiss our hypothesis that the more registers are included in
greater number of multiple scan-chains within particular scan-layout,
the better testability properties correspond to the scan-layout.",
  address="The University of Technology Košice",
  booktitle="Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics",
  chapter="22271",
  institution="The University of Technology Košice",
  year="2006",
  month="september",
  pages="308--313",
  publisher="The University of Technology Košice",
  type="conference paper"
}