Detail publikace

Methodology of Selecting Scan-Based Testability Improving Technique

KOTÁSEK, Z., STRNADEL, J., PEČENKA, T.

Originální název

Methodology of Selecting Scan-Based Testability Improving Technique

Anglický název

Methodology of Selecting Scan-Based Testability Improving Technique

Jazyk

en

Originální abstrakt

In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.

Anglický abstrakt

In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.

Dokumenty

BibTex


@inproceedings{BUT21466,
  author="Zdeněk {Kotásek} and Josef {Strnadel} and Tomáš {Pečenka}",
  title="Methodology of Selecting Scan-Based Testability Improving Technique",
  annote="In the paper, the solution of the problem of selecting the most optimal design-for-testability technique for register-transfer level digital circuits is demonstrated. A decision-making process that is able to solve the problem over a set of scan-based techniques is presented in the paper. The process decides among following testability improving techniques: identification of testable cores, covering of feedback loops by minimum set of scan registers, selection of registers into scan chains to achieve high level of parallelism during the test application.",
  address="University of West Hungary",
  booktitle="Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  chapter="21466",
  institution="University of West Hungary",
  year="2005",
  month="april",
  pages="186--189",
  publisher="University of West Hungary",
  type="conference paper"
}