Detail publikace

VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

STRNADEL, J.

Originální název

VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

Anglický název

VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements

Jazyk

en

Originální abstrakt

The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.

Anglický abstrakt

The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.

Dokumenty

BibTex


@inproceedings{BUT21464,
  author="Josef {Strnadel}",
  title="VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements",
  annote="The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.",
  address="University of West Hungary",
  booktitle="Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop",
  chapter="21464",
  institution="University of West Hungary",
  year="2005",
  month="april",
  pages="190--193",
  publisher="University of West Hungary",
  type="conference paper"
}