Detail publikace

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level

STRNADEL, J., KOTÁSEK, Z.

Originální název

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level

Anglický název

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level

Jazyk

en

Originální abstrakt

In the paper a new heuristic approach to the RTL testability analysis is presented. It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which satisfy concrete requirements in terms of the number of registers included into the scan chain, the area overhead and the test application time as a result of RTL testability analysis. The approach is based on the combination of analytical and evolutionary approaches at the RT level.

Anglický abstrakt

In the paper a new heuristic approach to the RTL testability analysis is presented. It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which satisfy concrete requirements in terms of the number of registers included into the scan chain, the area overhead and the test application time as a result of RTL testability analysis. The approach is based on the combination of analytical and evolutionary approaches at the RT level.

Dokumenty

BibTex


@inproceedings{BUT10243,
  author="Josef {Strnadel} and Zdeněk {Kotásek}",
  title="Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level",
  annote="In the paper a new heuristic approach to the RTL testability analysis is presented. It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which satisfy concrete requirements in terms of the number of registers included into the scan chain, the area overhead and the test application time as a result of RTL testability analysis. The approach is based on the combination of analytical and evolutionary approaches at the RT level.",
  address="IEEE Computer Society Press",
  booktitle="Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002",
  chapter="10243",
  institution="IEEE Computer Society Press",
  year="2002",
  month="september",
  pages="166--173",
  publisher="IEEE Computer Society Press",
  type="conference paper"
}