Detail publikace

Test scheduling for embedded systems

KOTÁSEK, Z., MIKA, D., STRNADEL, J.

Originální název

Test scheduling for embedded systems

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters.

Klíčová slova

TACG, genetic algorithm, embedded systems

Autoři

KOTÁSEK, Z., MIKA, D., STRNADEL, J.

Rok RIV

2003

Vydáno

1. 9. 2003

Nakladatel

IEEE Computer Society Press

Místo

Belek

ISBN

0-7695-2003-0

Kniha

Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003

Strany od

463

Strany do

467

Strany počet

5

BibTex

@inproceedings{BUT14193,
  author="Zdeněk {Kotásek} and Daniel {Mika} and Josef {Strnadel}",
  title="Test scheduling for embedded systems",
  booktitle="Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003",
  year="2003",
  pages="463--467",
  publisher="IEEE Computer Society Press",
  address="Belek",
  isbn="0-7695-2003-0"
}