Detail publikace

Testability Estimation Based on Controllability and Observability Parameters

PEČENKA, T. STRNADEL, J. KOTÁSEK, Z. SEKANINA, L.

Originální název

Testability Estimation Based on Controllability and Observability Parameters

Anglický název

Testability Estimation Based on Controllability and Observability Parameters

Jazyk

en

Originální abstrakt

In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The results gained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

Anglický abstrakt

In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The results gained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

Dokumenty

BibTex


@inproceedings{BUT22255,
  author="Tomáš {Pečenka} and Josef {Strnadel} and Zdeněk {Kotásek} and Lukáš {Sekanina}",
  title="Testability Estimation Based on Controllability and Observability Parameters",
  annote="In the paper a method for estimation the circuit testability on the Register
Transfer Level (RTL) is presented. The method allows to perform fast testability
estimation in linear time complexity (regarding the number of components and
interconnects of the circuit). Proposed approach is based on utilization of
controllability and observability measurement for estimation of overall circuit
testability. The application of developed method is demonstrated in a software
tool for the development of RTL benchmark circuits with predefined testability
properties. The results gained by our testability analysis method are compared
with the results of professional ATPG tool. Experiments show the good correlation
of the results obtained by our method and professional ATPG tool with
significantly lower time complexity when our algorithm is used.",
  address="IEEE Computer Society",
  booktitle="Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06)",
  chapter="22255",
  edition="IEEE CS",
  institution="IEEE Computer Society",
  year="2006",
  month="august",
  pages="504--514",
  publisher="IEEE Computer Society",
  type="conference paper"
}