Detail publikace

Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space

STRNADEL, J.

Originální název

Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space

Anglický název

Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space

Jazyk

en

Originální abstrakt

In the paper, novel sessionless approach to test-schedulling is presented. It utilizes so-called STEPs during special random-search based scheduling algorithm. The algorithm explores the state-space of so-called i-schedules whereas an i-schedule is an integer-vector encoded test-schedule represented by n-touple of STEPs. Proposed algorithm tries to link tests to STEPs in such a way there are no resource sharing conflicts in the best-found test schedule and hopefully, test schedule constraints are met maximally at minimal time and TAM values.

Anglický abstrakt

In the paper, novel sessionless approach to test-schedulling is presented. It utilizes so-called STEPs during special random-search based scheduling algorithm. The algorithm explores the state-space of so-called i-schedules whereas an i-schedule is an integer-vector encoded test-schedule represented by n-touple of STEPs. Proposed algorithm tries to link tests to STEPs in such a way there are no resource sharing conflicts in the best-found test schedule and hopefully, test schedule constraints are met maximally at minimal time and TAM values.

Dokumenty

BibTex 


@inproceedings{BUT22186,
  author="Josef {Strnadel}",
  title="Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space",
  annote="In the paper, novel sessionless approach to test-schedulling is presented. It
utilizes so-called STEPs during special random-search based scheduling algorithm.
The algorithm explores the state-space of so-called i-schedules whereas an
i-schedule is an integer-vector encoded test-schedule represented by n-touple of
STEPs. Proposed algorithm tries to link tests to STEPs in such a way there are no
resource sharing conflicts in the best-found test schedule and hopefully, test
schedule constraints are met maximally at minimal time and TAM values.",
  address="Czech Technical University Publishing House",
  booktitle="Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  chapter="22186",
  institution="Czech Technical University Publishing House",
  year="2006",
  month="april",
  pages="161--162",
  publisher="Czech Technical University Publishing House",
  type="conference paper"
}