Detail publikace

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

STRNADEL, J.

Originální název

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

Anglický název

Testability Analysis and Improvements of Register-Transfer Level Digital Circuits

Jazyk

en

Originální abstrakt

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

Anglický abstrakt

The paper presents novel testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on virtual port conception is utilized to describe the information and proposed testability analysis method. In order to be effective, the method is based on the idea of searching two special digraphs developed for the purpose. Experimental results gained by the method are presented and compared with results of existing methods.

Dokumenty

BibTex


@article{BUT45082,
  author="Josef {Strnadel}",
  title="Testability Analysis and Improvements of Register-Transfer Level Digital Circuits",
  annote="The paper presents novel testability analysis method applicable to
regis-ter-transfer level digital circuits.
It is shown if each module stored in a design library is equipped both with
information related to design
and information related to testing, then more accurate testability results can be
achieved. A mathematical model based on virtual port conception is utilized to
describe the information and proposed testability analysis method.
In order to be effective, the method is based on the idea of searching two
special digraphs developed for the purpose.
Experimental results gained by the method are presented
and compared with results of existing methods.",
  chapter="45082",
  journal="Computing and Informatics",
  number="5",
  volume="25",
  year="2006",
  month="november",
  pages="441--464",
  type="journal article - other"
}