Publication detail

An FPGA-Based Priority Packet Queues

SMÉKAL, D. NÉMETH, F. DVOŘÁK, J.

Original Title

An FPGA-Based Priority Packet Queues

English Title

An FPGA-Based Priority Packet Queues

Type

conference paper

Language

en

Original Abstract

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.

English abstract

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.

Keywords

Packet Queues; Quality of Service; Shaping Throughput; Limiter; Tocken Bucket; VHDL; FPGA; Netcope Development Kit

Released

29.10.2019

Publisher

IFAC-PapersOnLine

Location

High Tatras, Slovakia

Pages from

377

Pages to

381

Pages count

5

URL

BibTex


@inproceedings{BUT159155,
  author="David {Smékal} and František {Németh} and Jan {Dvořák}",
  title="An FPGA-Based Priority Packet Queues",
  annote="Paper deals with issues and problems of packet queue management in high speed packet networks. Design
implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism
for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on
the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.",
  address="IFAC-PapersOnLine",
  booktitle="16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019",
  chapter="159155",
  doi="10.1016/j.ifacol.2019.12.689",
  edition="52",
  howpublished="online",
  institution="IFAC-PapersOnLine",
  number="27",
  year="2019",
  month="october",
  pages="377--381",
  publisher="IFAC-PapersOnLine",
  type="conference paper"
}