Detail publikace

An FPGA-Based Priority Packet Queues

Originální název

An FPGA-Based Priority Packet Queues

Anglický název

An FPGA-Based Priority Packet Queues

Jazyk

en

Originální abstrakt

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.

Anglický abstrakt

Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.

BibTex


@inproceedings{BUT159155,
  author="David {Smékal} and František {Németh} and Jan {Dvořák}",
  title="An FPGA-Based Priority Packet Queues",
  annote="Paper deals with issues and problems of packet queue management in high speed packet networks. Design
implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism
for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on
the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.",
  address="IFAC-PapersOnLine",
  booktitle="16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019",
  chapter="159155",
  howpublished="online",
  institution="IFAC-PapersOnLine",
  number="12",
  year="2019",
  month="october",
  pages="1--5",
  publisher="IFAC-PapersOnLine",
  type="conference paper"
}