Publication detail

Packet Processing on FPGA SoC with DPDK

KOŘENEK, J. VIKTORIN, J.

Original Title

Packet Processing on FPGA SoC with DPDK

Type

conference paper

Language

English

Original Abstract

One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. The ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.

Keywords

DPDK, FPGA, SoC, ARM, packet processing

Authors

KOŘENEK, J.; VIKTORIN, J.

Released

29. 8. 2016

Publisher

École Polytechnique Fédérale de Lausanne

Location

Lausanne

ISBN

978-2-8399-1844-2

Book

26th International Conference on Field-Programmable Logic and Applications

Pages from

578

Pages to

579

Pages count

2

URL

http://ieeexplore.ieee.org/document/7577395/

BibTex

@inproceedings{BUT130979,
  author="Jan {Kořenek} and Jan {Viktorin}",
  title="Packet Processing on FPGA SoC with DPDK",
  booktitle="26th International Conference on Field-Programmable Logic and Applications",
  year="2016",
  pages="578--579",
  publisher="École Polytechnique Fédérale de Lausanne",
  address="Lausanne",
  doi="10.1109/FPL.2016.7577395",
  isbn="978-2-8399-1844-2",
  url="http://ieeexplore.ieee.org/document/7577395/"
}