Detail publikace

Packet Processing on FPGA SoC with DPDK

KOŘENEK, J. VIKTORIN, J.

Originální název

Packet Processing on FPGA SoC with DPDK

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. The ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.

Klíčová slova

DPDK, FPGA, SoC, ARM, packet processing

Autoři

KOŘENEK, J.; VIKTORIN, J.

Vydáno

29. 8. 2016

Nakladatel

École Polytechnique Fédérale de Lausanne

Místo

Lausanne

ISBN

978-2-8399-1844-2

Kniha

26th International Conference on Field-Programmable Logic and Applications

Strany od

578

Strany do

579

Strany počet

2

URL

http://ieeexplore.ieee.org/document/7577395/

BibTex

@inproceedings{BUT130979,
  author="Jan {Kořenek} and Jan {Viktorin}",
  title="Packet Processing on FPGA SoC with DPDK",
  booktitle="26th International Conference on Field-Programmable Logic and Applications",
  year="2016",
  pages="578--579",
  publisher="École Polytechnique Fédérale de Lausanne",
  address="Lausanne",
  doi="10.1109/FPL.2016.7577395",
  isbn="978-2-8399-1844-2",
  url="http://ieeexplore.ieee.org/document/7577395/"
}