Detail publikace

Serial IIR Filter Structure Generator for ASICs

Originální název

Serial IIR Filter Structure Generator for ASICs

Anglický název

Serial IIR Filter Structure Generator for ASICs

Jazyk

en

Originální abstrakt

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Anglický abstrakt

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

BibTex


@article{BUT96418,
  author="Marián {Pristach} and Lukáš {Fujcik}",
  title="Serial IIR Filter Structure Generator for ASICs",
  annote="The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.",
  address="Západočeská univerzita v Plzni",
  chapter="96418",
  institution="Západočeská univerzita v Plzni",
  number="6",
  volume="2012",
  year="2012",
  month="december",
  pages="1--4",
  publisher="Západočeská univerzita v Plzni",
  type="journal article - other"
}