Detail publikace

Design and Implementation of a 0.3-V Differential Difference Amplifier

KHATEB, F. KULEJ, T.

Originální název

Design and Implementation of a 0.3-V Differential Difference Amplifier

Anglický název

Design and Implementation of a 0.3-V Differential Difference Amplifier

Jazyk

en

Originální abstrakt

A new silicon realization of an ultra low voltage (LV) and ultra low power (LP) differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven (BD) differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate (SR) of 1.55 V/ms at 20 pF load capacitance, while consuming only 22nW of power. An instrumentation amplifier (IA) based on the proposed DDA showed the THD of 0.5 % for Vin=50mVpp, and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 um CMOS process from TSMC. Chip test results agree well with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.

Anglický abstrakt

A new silicon realization of an ultra low voltage (LV) and ultra low power (LP) differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven (BD) differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate (SR) of 1.55 V/ms at 20 pF load capacitance, while consuming only 22nW of power. An instrumentation amplifier (IA) based on the proposed DDA showed the THD of 0.5 % for Vin=50mVpp, and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 um CMOS process from TSMC. Chip test results agree well with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.

Dokumenty

BibTex


@article{BUT148750,
  author="Fabian {Khateb} and Tomasz {Kulej}",
  title="Design and Implementation of a 0.3-V Differential Difference Amplifier",
  annote="A new silicon realization of an ultra low voltage (LV) and ultra low power (LP) differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven (BD) differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate (SR) of 1.55 V/ms  at 20 pF load capacitance, while consuming only 22nW of power. An instrumentation amplifier (IA) based on the proposed DDA showed the THD of 0.5 % for Vin=50mVpp, and  the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 um CMOS process from TSMC. Chip test results agree well with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.",
  address="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  chapter="148750",
  doi="10.1109/TCSI.2018.2866179",
  howpublished="print",
  institution="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  number="2, IF: 3.934",
  volume="66",
  year="2019",
  month="march",
  pages="513--523",
  publisher="IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",
  type="journal article in Web of Science"
}