Detail publikace

Design and implementation of sub 0.5-V OTAs in 0.18 um CMOS

Originální název

Design and implementation of sub 0.5-V OTAs in 0.18 um CMOS

Anglický název

Design and implementation of sub 0.5-V OTAs in 0.18 um CMOS

Jazyk

en

Originální abstrakt

A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain bandwidth product (GBW), slew rate (SR), circuit sensitivity to process/mismatch variations and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18 um n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

Anglický abstrakt

A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain bandwidth product (GBW), slew rate (SR), circuit sensitivity to process/mismatch variations and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18 um n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

BibTex


@article{BUT144890,
  author="Tomasz {Kulej} and Fabian {Khateb}",
  title="Design and implementation of sub 0.5-V OTAs in 0.18 um CMOS",
  annote="A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain bandwidth product (GBW), slew rate (SR), circuit sensitivity to process/mismatch variations and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18 um n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.",
  address="WILEY-BLACKWELL",
  chapter="144890",
  doi="10.1002/cta.2465",
  howpublished="print",
  institution="WILEY-BLACKWELL",
  number="6,  IF: 1.444",
  volume="46",
  year="2018",
  month="january",
  pages="1129--1143",
  publisher="WILEY-BLACKWELL",
  type="journal article in Web of Science"
}