Detail publikace

Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS

Originální název

Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS

Anglický název

Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS

Jazyk

en

Originální abstrakt

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 um CMOS process, the proposed LTA circuit in a two-input version consume 3.0 uW from a 0.5 V supply and provide 10 us crossover recovery time for a 1 pF load capacitance.

Anglický abstrakt

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 um CMOS process, the proposed LTA circuit in a two-input version consume 3.0 uW from a 0.5 V supply and provide 10 us crossover recovery time for a 1 pF load capacitance.

BibTex


@article{BUT135051,
  author="Tomasz {Kulej} and Fabian {Khateb}",
  title="Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS",
  annote="The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 um CMOS process, the proposed LTA circuit in a two-input version consume 3.0 uW from a 0.5 V supply and provide 10 us crossover recovery time for a 1 pF load capacitance.",
  address="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  chapter="135051",
  doi="10.1016/j.aeue.2017.04.032",
  howpublished="print",
  institution="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  number=", IF: 1.147",
  volume="2017 (77)",
  year="2017",
  month="april",
  pages="67--75",
  publisher="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  type="journal article in Web of Science"
}