Publication detail

Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS

KULEJ, T. KHATEB, F.

Original Title

Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS

Type

journal article in Web of Science

Language

English

Original Abstract

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 mu m CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 mu W from a 0.5 V supply and provides 10 mu s crossover recovery time for a 1 pF load capacitance.

Keywords

Min/Max circuits; Winner take all; Loser take all; Bulk-driven; Low-voltage; Low-power; Voltage follower.

Authors

KULEJ, T.; KHATEB, F.

Released

25. 4. 2017

Publisher

ELSEVIER GMBH, URBAN & FISCHER VERLAG

Location

Germany

ISBN

1434-8411

Periodical

AEU - International Journal of Electronics and Communications

Year of study

2017 (77)

Number

, IF: 1.147

State

Federal Republic of Germany

Pages from

67

Pages to

75

Pages count

9

URL

http://dx.doi.org/10.1016/j.aeue.2017.04.032

BibTex

@article{BUT135051,
  author="Tomasz {Kulej} and Fabian {Khateb}",
  title="Sub 0.5-V Bulk-driven LTA in 0.18 um CMOS",
  journal="AEU - International Journal of Electronics and Communications",
  year="2017",
  volume="2017 (77)",
  number=", IF: 1.147",
  pages="67--75",
  doi="10.1016/j.aeue.2017.04.032",
  issn="1434-8411",
  url="http://dx.doi.org/10.1016/j.aeue.2017.04.032"
}