Detail publikace

Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor

Originální název

Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor

Anglický název

Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor

Jazyk

en

Originální abstrakt

A digitally programmable low-voltage highly linear transconductor (Gm stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of +-0.5V and consumes 36uW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35um CMOS AMIS process with total chip area 213um x 266um. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.

Anglický abstrakt

A digitally programmable low-voltage highly linear transconductor (Gm stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of +-0.5V and consumes 36uW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35um CMOS AMIS process with total chip area 213um x 266um. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.

BibTex


@article{BUT113856,
  author="Fabian {Khateb} and Abhirup {Lahiri} and Costas {Psychalinos} and Montree {Kumngern} and Tomasz {Kulej}",
  title="Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor",
  annote="A digitally programmable low-voltage highly linear transconductor (Gm stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of +-0.5V and consumes 36uW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35um CMOS AMIS process with total chip area 213um x 266um. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.",
  address="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  chapter="113856",
  doi="10.1016/j.aeue.2015.03.005",
  institution="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  number="7, IF: 0.601",
  volume="2015 (69)",
  year="2015",
  month="march",
  pages="1010--1017",
  publisher="ELSEVIER GMBH, URBAN & FISCHER VERLAG",
  type="journal article in Web of Science"
}