Detail publikace

Comparative study of Sub-volt Differential Difference Current Conveyors

Originální název

Comparative study of Sub-volt Differential Difference Current Conveyors

Anglický název

Comparative study of Sub-volt Differential Difference Current Conveyors

Jazyk

en

Originální abstrakt

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limits their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG) technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at +-300 mV supply voltage and 18.5 uW power consumption. The simulation results using 0.18 um CMOS n-Well process from TSMC show the features of the proposed circuits.

Anglický abstrakt

Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limits their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG) technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at +-300 mV supply voltage and 18.5 uW power consumption. The simulation results using 0.18 um CMOS n-Well process from TSMC show the features of the proposed circuits.

BibTex


@article{BUT100981,
  author="Fabian {Khateb} and Winai {Jaikla} and Montree {Kumngern} and Pipat {Prommee}",
  title="Comparative study of Sub-volt Differential Difference Current Conveyors",
  annote="Enhancing the performances of analog circuits with sub-volt supplies becomes a great challenge for circuit designers. Techniques such as bulk-driven (BD) and quasi-floating gate (QFG) count among the suitable ones for ultra-low voltage (ULV) operation capability with extended input voltage range and simple CMOS circuitry. However, in comparison to the conventional gate-driven (GD) MOS transistor (MOST), these techniques suffer from several disadvantages such as low transconductance value and bandwidth that limits their applicability for some applications. Therefore, the idea of merging the BD and QFG techniques to eliminate their drawbacks appears as efficacious solution. This new merging is named bulk-driven quasi-floating gate (BD-QFG) technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-QFG techniques. The significant increment of the transconductance and the bandwidth values of the BD-QFG are clearly observed. The proposed CMOS structures of the DDCCs work at +-300 mV supply voltage and 18.5 uW power consumption. The simulation results using 0.18 um CMOS n-Well process from TSMC show the features of the proposed circuits.",
  address="ELSEVIER",
  chapter="100981",
  doi="10.1016/j.mejo.2013.08.015",
  institution="ELSEVIER",
  number="12, IF: 0,912",
  volume="2013 (44)",
  year="2013",
  month="december",
  pages="1278--1284",
  publisher="ELSEVIER",
  type="journal article in Web of Science"
}