Detail publikace

Serial IIR Filter Structure Generator for ASICs

PRISTACH, M. FUJCIK, L.

Originální název

Serial IIR Filter Structure Generator for ASICs

Typ

článek v časopise - ostatní, Jost

Jazyk

angličtina

Originální abstrakt

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Klíčová slova

application specific integration circuits, hardware description language, infinite impulse response filter, multiply and accumulate unit

Autoři

PRISTACH, M.; FUJCIK, L.

Rok RIV

2012

Vydáno

31. 12. 2012

Nakladatel

Západočeská univerzita v Plzni

Místo

Plzeň

ISSN

1802-4564

Periodikum

ElectroScope - http://www.electroscope.zcu.cz

Ročník

2012

Číslo

6

Stát

Česká republika

Strany od

1

Strany do

4

Strany počet

4

BibTex

@article{BUT96418,
  author="Marián {Pristach} and Lukáš {Fujcik}",
  title="Serial IIR Filter Structure Generator for ASICs",
  journal="ElectroScope - http://www.electroscope.zcu.cz",
  year="2012",
  volume="2012",
  number="6",
  pages="1--4",
  issn="1802-4564"
}