Publication detail

Serial IIR Filter Structure Generator for ASICs

PRISTACH, M. FUJCIK, L.

Original Title

Serial IIR Filter Structure Generator for ASICs

English Title

Serial IIR Filter Structure Generator for ASICs

Type

journal article - other

Language

en

Original Abstract

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

English abstract

The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.

Keywords

application specific integration circuits, hardware description language, infinite impulse response filter, multiply and accumulate unit

RIV year

2012

Released

31.12.2012

Publisher

Západočeská univerzita v Plzni

Location

Plzeň

Pages from

1

Pages to

4

Pages count

4

BibTex


@article{BUT96418,
  author="Marián {Pristach} and Lukáš {Fujcik}",
  title="Serial IIR Filter Structure Generator for ASICs",
  annote="The paper presents generator of an infinite impulse response (IIR) digital filter structure for implementation in application specific integration circuits (ASICs). The paper describes the filter architecture with serial calculation. The serial architecture utilizes one shared multiply and accumulate (MAC) unit in order to achieve minimal area on chip. Software in C++ language was written for automatic filter generation. The software generates fully synthesizable VHDL description of filter, batch file for simulator and test-bench file for automatic filter verification from the filter specification file.",
  address="Západočeská univerzita v Plzni",
  chapter="96418",
  institution="Západočeská univerzita v Plzni",
  number="6",
  volume="2012",
  year="2012",
  month="december",
  pages="1--4",
  publisher="Západočeská univerzita v Plzni",
  type="journal article - other"
}