Detail publikace

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

Originální název

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

Anglický název

Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures

Jazyk

en

Originální abstrakt

In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although proposed circuits are very similar, significant differences were demonstrated, namely in the number of unique designs they can implement, the sensitiveness of functions to the inversions in the configuration bitstream and the average number of generations needed to find a target function. These findings are quite unintuitive. Once important (sensitive) bits of the reconfigurable circuit are identified, evolutionary algorithm can incorporate this knowledge. We believe that the proposed type of analysis can help those designers who develop new reconfigurable circuits for evolvable hardware applications.

Anglický abstrakt

In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although proposed circuits are very similar, significant differences were demonstrated, namely in the number of unique designs they can implement, the sensitiveness of functions to the inversions in the configuration bitstream and the average number of generations needed to find a target function. These findings are quite unintuitive. Once important (sensitive) bits of the reconfigurable circuit are identified, evolutionary algorithm can incorporate this knowledge. We believe that the proposed type of analysis can help those designers who develop new reconfigurable circuits for evolvable hardware applications.

BibTex


@inproceedings{BUT34273,
  author="Lukáš {Sekanina} and Petr {Mikušek}",
  title="Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures",
  annote="In this paper we propose three small instances of a reconfigurable circuit and
analyze their properties using the brute force method and evolutionary algorithm.
Although proposed circuits are very similar, significant differences were
demonstrated, namely in the number of unique designs they can implement, the
sensitiveness of functions to the inversions in the configuration bitstream and
the average number of generations needed to find a target function. These
findings are quite unintuitive. Once important (sensitive) bits of the
reconfigurable circuit are identified, evolutionary algorithm can incorporate
this knowledge. We believe that the proposed type of analysis can help those
designers who develop new reconfigurable circuits for evolvable hardware
applications.",
  address="Springer Verlag",
  booktitle="Applications of Evolutionary Computing",
  chapter="34273",
  edition="Lecture Notes in Computer Science",
  howpublished="print",
  institution="Springer Verlag",
  journal="Lecture Notes in Computer Science (IF 0,513)",
  year="2008",
  month="march",
  pages="144--153",
  publisher="Springer Verlag",
  type="conference paper"
}