Detail publikace

Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

VÁVRA, J. BIOLEK, D. KOLKA, Z.

Originální název

Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

Typ

článek ve sborníku ve WoS nebo Scopus

Jazyk

angličtina

Originální abstrakt

A procedure supporting the design and optimization of analog circuits is described. It is based on symbolic analysis of the respective linearized model with the aim of revealing the major factors influencing the non-ideal behavior of the designed device. SNAP 3, a powerful tool for the approximate symbolic analysis of circuits containing assorted types of active building blocks, plays a key role in this process. The procedure is illustrated on the example of inductance multiplier.

Klíčová slova

approximate symbolic analysis; transfer function; impedance; inductance multiplier

Autoři

VÁVRA, J.; BIOLEK, D.; KOLKA, Z.

Vydáno

2. 7. 2018

Nakladatel

IEEE

Místo

USA

ISBN

978-1-5386-5152-0

Kniha

15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018)

Strany od

265

Strany do

268

Strany počet

4

URL

https://ieeexplore.ieee.org/document/8434846

BibTex

@inproceedings{BUT149252,
  author="Jiří {Vávra} and Dalibor {Biolek} and Zdeněk {Kolka}",
  title="Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms",
  booktitle="15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018)",
  year="2018",
  pages="265--268",
  publisher="IEEE",
  address="USA",
  doi="10.1109/SMACD.2018.8434846",
  isbn="978-1-5386-5152-0",
  url="https://ieeexplore.ieee.org/document/8434846"
}