Publication detail

Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

VÁVRA, J. BIOLEK, D. KOLKA, Z.

Original Title

Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms

Type

conference paper

Language

English

Original Abstract

A procedure supporting the design and optimization of analog circuits is described. It is based on symbolic analysis of the respective linearized model with the aim of revealing the major factors influencing the non-ideal behavior of the designed device. SNAP 3, a powerful tool for the approximate symbolic analysis of circuits containing assorted types of active building blocks, plays a key role in this process. The procedure is illustrated on the example of inductance multiplier.

Keywords

approximate symbolic analysis; transfer function; impedance; inductance multiplier

Authors

VÁVRA, J.; BIOLEK, D.; KOLKA, Z.

Released

2. 7. 2018

Publisher

IEEE

Location

USA

ISBN

978-1-5386-5152-0

Book

15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018)

Pages from

265

Pages to

268

Pages count

4

URL

https://ieeexplore.ieee.org/document/8434846

BibTex

@inproceedings{BUT149252,
  author="Jiří {Vávra} and Dalibor {Biolek} and Zdeněk {Kolka}",
  title="Design and Error Analysis of Inductance Multiplier via Symbolic Algorithms",
  booktitle="15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2018)",
  year="2018",
  pages="265--268",
  publisher="IEEE",
  address="USA",
  doi="10.1109/SMACD.2018.8434846",
  isbn="978-1-5386-5152-0",
  url="https://ieeexplore.ieee.org/document/8434846"
}