SECREDAS

angličtina

Fiedler Petr, doc. Ing., Ph.D. - hlavní řešitel
Arm Jakub, Ing., Ph.D. - spoluřešitel
Baštán Ondřej, Ing. - spoluřešitel
Benešl Tomáš, Ing. - spoluřešitel
Bradáč Zdeněk, doc. Ing., Ph.D. - spoluřešitel
Jirgl Miroslav, Ing., Ph.D. - spoluřešitel
Kaczmarczyk Václav, Ing., Ph.D. - spoluřešitel
Mihálik Ondrej, Ing. - spoluřešitel
Michalík David, Ing. - spoluřešitel

Středoevropský technologický institut VUT
- odpovědné pracoviště (12.09.2017 - nezadáno)
Ústav automatizace a měřicí techniky
- spolupříjemce (01.04.2018 - 31.03.2021)
Kybernetika pro materiálové vědy
- příjemce (01.04.2018 - 31.03.2021)

Evropská unie - Horizon 2020

- plně financující (2018-05-01 - 2021-04-30)
Ministerstvo školství, mládeže a tělovýchovy ČR - Společná technologická iniciativa ECSEL

- plně financující (2018-09-21 - 2021-04-30)

LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018. p. 1-4. ISBN: 978-1-5386-7312-6.
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LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020. p. 24-28. ISBN: 978-1-7281-9899-6.
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PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 63-69. ISBN: 978-1-5386-5710-2.
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PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018. p. 129-134. ISBN: 978-1-5386-5710-2.
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LOJDA, J.; KOTÁSEK, Z. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. In Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018. s. 5-8. ISBN: 978-80-261-0814-6.
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PÁNEK, R. Metodika návrhu řadiče rekonfigurace pro Systémy odolné proti poruchám. In Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018. s. 21-24. ISBN: 978-80-261-0814-6.
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ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018. p. 331-336. ISBN: 978-1-5386-5710-2.
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PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 97-100. ISBN: 978-1-7281-1756-0.
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LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 93-96. ISBN: 978-1-7281-1756-0.
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MICHALÍK, D.; MIHÁLIK, O.; JIRGL, M.; FIEDLER, P. Driver Behaviour Modeling with Vehicle Driving Simulator. In 16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019. IFAC-PapersOnLine (ELSEVIER). 2019. p. 180-185. ISSN: 2405-8963.
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JIRGL, M.; BRADÁČ, Z.; FIEDLER, P. Adaptive Human Control Model and its Usability in Modeling of Human-in-the-loop Cyber Physical Systems. In 16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019. IFAC-PapersOnLine (ELSEVIER). ELSEVIER, 2019. p. 415-420. ISSN: 2405-8963.
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JIRGL, M.; FIEDLER, P.; BRADÁČ, Z. Using Matlab-based Driving Simulator for Human Factor Assessment. In 16th IFAC Conference on Programmable Devices and Embedded Systems PDeS 2019. IFAC-PapersOnLine (ELSEVIER). ELSEVIER, 2019. p. 27-32. ISSN: 2405-8963.
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BAŠTÁN, O.; FIEDLER, P.; BENEŠL, T.; ARM, J. Redundancy as an important source of resilience in the Safety II concept. In 16th IFAC INTERNATIONAL CONFERENCE on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS - PDeS 2019. IFAC-PapersOnLine (ELSEVIER). Tatranská Lomnica: 2019. p. 382-387. ISSN: 2405-8963.
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KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Detecting hard synapses faults in artificial neural networks. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019. p. 1-6. ISBN: 978-1-7281-1756-0.
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ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. p. 506-513. ISBN: 978-1-7281-2861-0.
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ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Smart Electronic Locks and Their Reliability. In Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. p. 4-5. ISBN: 978-80-01-06607-2.
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PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020. p. 1-4. ISBN: 978-1-7281-3427-7.
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LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020. p. 1-4. ISBN: 978-1-7281-9938-2.
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JIRGL, M.; BOŘIL, J.; JALOVECKÝ, R. Statistical Evaluation of Pilot’s Behavior Models Parameters Connected to Military Flight Training. ENERGIES, 2020, vol. 13, no. 17, p. 1-13. ISSN: 1996-1073.
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PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. In 2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers. Hsinchu: IEEE Computer Society, 2020. p. 121-124. ISBN: 978-1-7281-6083-2.
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LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020. p. 680-683. ISBN: 978-1-7281-9535-3.
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LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 80-86. ISBN: 978-1-5386-5710-2.
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