Course detail

Design of Computer Systems

FIT-INPAcad. year: 2019/2020

Principles of a processor. Von Neumann computer. Data types, formats and coding. Instructions, formats, coding and addressing, instruction set architecture. VHDL models of algorithms and subsystems. Pipelining. Arithmetic and logic operations. Sequencer: basic function, hard-wired and microprogram implementation. Memories: types, organization, control. Memory hierarchy, cache memory. Peripheral units, buses and bus control. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.

Learning outcomes of the course unit

Students are able to describe the functionality of the operation, memory and control units and their communication in a computer. They are familiar with VHDL.
Understanding of development trends and possibilities of computer technology.


Not applicable.


Boolean algebra, basics of electrical circuits, basic computer elements, design of combinatorial and sequential circuits.

Recommended optional programme components

Not applicable.

Recommended or required reading

Drábek, V.: Výstavba počítačů, skripta VUT v Brně, PC-DIR, Brno, 1995.
Pinker, J., Poupa, M.: Číslicové systémy a jazyk VHDL, BEN - technická literatura, Praha, 2006. (CS)
Hennessy, J. L., Patterson, D. A.: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996, popř. nové edice, např. 5th ed. z r. 2012. (EN)
Materials presented at course, available on the course website. (EN)
Hamacher, C., Vranesic, Z., Zaky, S.,  N. Manjikian: Computer Organization and Embedded Systems, 6th edition, McGraw Hill Education, 2011, ISBN-13: 978-0073380650

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Written final exam, mid-term exam and submitting projects in due dates.
Exam prerequisites:
For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.

Language of instruction

Czech, English

Work placements

Not applicable.


To give the students knowledge of organization and functioning of a (single core) processor, in particular, the principles of the operation, memory and control units, the algorithms with fixed and floating point number systems, the subsystem communication level, and integration of the processor to a parallel system.

Specification of controlled education, way of implementation and compensation for absences

Within this course, attendance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 20. Otherwise, no points will be assigned to a student. In the case of a reported barrier preventing the student to perform the scheduled activity, the guarantor can allow the student to perform this activity on an alternative date.

Classification of course in study plans

  • Programme BIT Bachelor's, 2. year of study, winter semester, 6 credits, compulsory

  • Programme IT-BC-3 Bachelor's

    branch BIT , 2. year of study, winter semester, 6 credits, compulsory

Type of course unit



39 hours, optionally

Teacher / Lecturer


  • Introduction, processor and its function.
  • Data representation.
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipeline processing.
  • Algorithms of fixed-point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controllers.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.

Fundamentals seminar

12 hours, compulsory

Teacher / Lecturer


  • VHDL - introduction
  • VHDL - synthesizable code
  • Introduction to FITkit
  • Processor in VHDL
  • Huffman code, Hamming code
  • Modular arithmetic, adders
  • Multipliers
  • Division
  • Iterative algorithms
  • Performance evaluation, reliability
  • Parallel Architectures


14 hours, compulsory

Teacher / Lecturer


  • Two projects will be assigned during the semester.