Czech

7

Not applicable.

Students must have a knowledge of mathematics and electrical circuits at the level of the 1st year Bachelor studies. Work in the laboratory is conditioned by a valid qualification of a "trained worker" according to decree 50/1978 Coll. This qualification students must obtain before the start of teaching. Information on this qualification is given in the Dean's Directive Familiarization of students with safety regulations.

Up to 40 points for the submission of elaborated theoretical preparations for laboratory tasks and a demonstration of the functional implementation of the practical jobs of each task on the laboratory equipment. The condition for granting the credit is the submission of the elaborated theoretical preparations and the implementation of mandatory practical assignments of all laboratory tasks.
Up to 60 points for the final written exam.
The content and forms of instruction in the evaluated course are specified by a regulation issued by the lecturer responsible for the course and updated for every academic year.

To have basic knowledge of logic systems and their design, construction, testing and practical usage.
To acquaint students with basics of the VHDL language intended for hardware description.
To gain basic knowledge of methods for description, analysis and design of combinational and sequential logic circuits.
To use the VHDL language for simulation and testing of logic systems.

The absolvent has knowledge in the following areas:
- characteristics of basic logic circuits and systems,
- basics of VHDL language for hardware description,
- principles of analysis, design and implementation of combinational and sequential logic circuits,
- principles of designing, construction, testing and practical use logical systems.
The absolvent is able to:
- use a development environment for computer aided design of hardware using HDL languages,
- use VHDL language for modeling, simulation and synthesis of digital systems,
- implement basic logic systems for development kit containing a gate array.

Not applicable.

Not applicable.

KOLOUCH, J.: Programovatelné logické obvody - Přednášky [Skriptum FEKT VUT v Brně] Brno 2005 (CS)

PINKER, J.; POUPA, M: Číslicové systémy a jazyk VHDL. 2006, ISBN 80-7300-198-5 (CS)

eLearning: currently opened course

39 hours, compulsory

eLearning: currently opened course