Course detail

Functional Verification of Digital Systems

FIT-FVSAcad. year: 2018/2019

Importance of functional verification. Requirements specification and verification plan. Simulation and creating testbenches. Functional verification and its methods (pseudo-random stimuli generation, coverage-driven verification, asserion-based verification, self-checking mechanisms). Verification methodologies and SystemVerilog language. Reporting and correction of errors. Emulation and FPGA prototyping.

Learning outcomes of the course unit

A student will understand the main techniques of functional verification of digital systems: simulation, functional verification and its methods, emulation and prototyping. He/she will be able to analyze source codes and outputs of verification tools, to localize errors and to handle their correction. He/she will master creating basic verification environments in SystemVerilog language according to OVM/UVM verification methodology.
Acquired knowledge about the significance and possibilities of using functional verification methods within the development of digital systems and about their growing use in practice.

Prerequisites

Digital system design, basic programming skills.

Co-requisites

Not applicable.

Recommended optional programme components

Not applicable.

Recommended or required reading

Přednáškové materiály v elektronické formě.

  • Myer, A.: Principles of Functional Verification, Newnes, USA, 2003. ISBN: 0750676175.
  • Bergeron, J.: Writing Testbenches using SystemVerilog, Springer, USA, 2006. ISBN: 0387292217
  • Spear, Ch., Tumbush, G., SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, USA, 2012. ISBN: 1461407141.
  • Haque, F., Michelson, J., Khan, K.: The Art of Verification with SystemVerilog Assertions, Verification Central, USA, 2006. ISBN: 0971199418.
  • Amos, D., Lesea, A., Richter, R.: FPGA-Based Prototyping Methodology Manual: Best Practices in Design-For-Prototyping, Synopsys Press, USA,2011. ISBN: 1617300047.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Labs and project in due dates.
Exam prerequisites:
Requirements for class accreditation are not defined.

Language of instruction

Czech

Work placements

Not applicable.

Course curriculum

    Syllabus of lectures:
    1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
    2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
    3. Introduction to functional verification. Functional verification techniques.
    4. Verification methodologies. HVL languages.
    5. Pseudo-random stimuli generation, direct tests, constraints.
    6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
    7. Self-checking mechanisms.
    8. Assertions. Assertion languages. Errors reporting.
    9. Assertion-based verification.
    10. Emulation and prototyping.
    11. Hardware debugging.
    12. Industry lecture.
    13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

    Syllabus of laboratory exercises:
    1. Creating testbench for arithmetic-logic unit (ALU).
    2. Creating verification environment for ALU.
    3. Coverage-driven verification of ALU.
    4. Assertion-based verification of ALU.

    Syllabus - others, projects and individual work of students:
    Design and implementation of verification environment for a selected digital systém.

Aims

Overview about functional verification of digital systems. The attention is paid to creating testbenches and functional verification environments according to widely used verification methodologies (OVM, UVM) and to emulation. The aim is to understand how to detect and localize errors in digital systems and how to handle them properly.

Classification of course in study plans

  • Programme IT-MGR-2 Master's

    branch MBI , any year of study, summer semester, 5 credits, optional
    branch MPV , any year of study, summer semester, 5 credits, optional
    branch MGM , any year of study, summer semester, 5 credits, optional
    branch MSK , any year of study, summer semester, 5 credits, optional
    branch MIS , any year of study, summer semester, 5 credits, optional
    branch MBS , any year of study, summer semester, 5 credits, optional
    branch MIN , any year of study, summer semester, 5 credits, optional
    branch MMI , any year of study, summer semester, 5 credits, optional
    branch MMM , any year of study, summer semester, 5 credits, optional

Type of course unit

 

Lecture

26 hours, optionally

Teacher / Lecturer

Syllabus


  1. History of functional verification, HDL and HVL languages. Requirements specification and the verification plan.
  2. Testing digital systems using simulation. VHDL language. Creating testbenches. HDL simulators.
  3. Introduction to functional verification. Functional verification techniques.
  4. Verification methodologies. HVL languages.
  5. Pseudo-random stimuli generation, direct tests, constraints.
  6. Coverage-driven verification. Coverage metrics. Coverage measurement and analysis.
  7. Self-checking mechanisms.
  8. Assertions. Assertion languages. Errors reporting.
  9. Assertion-based verification.
  10. Emulation and prototyping.
  11. Hardware debugging.
  12. Industry lecture.
  13. Special cases in verification of digital systems. Other verification approaches. Challenges and open problems in verification.

Laboratory exercise

8 hours, compulsory

Teacher / Lecturer

Syllabus


  1. Creating testbench for a selected digital system.
  2. Creating verification environment for a selected digital system.

  3. Coverage-driven verification of a selected digital system.
  4. Assertion-based verification of a selected digital system.

Project

18 hours, compulsory

Teacher / Lecturer

Syllabus

Design and implementation of verification environment for a selected digital system.

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