Course detail

Processor Architecture

FIT-ACHAcad. year: 2013/2014

The course covers architecture of universal as well as special-purpose processors. Instruction-level parallelism (ILP) is studied on scalar, superscalar and VLIW processors. Then the processors with thread-level parallelism (TLP) are discussed. Data parallelism is illustrated on vector processors, SIMD streaming instructions and on graphical processors (SIMT). Parallelization of numerical calculations for GPU is also covered (CUDA). Other specialized processors covered in the course are network processors, DSPs, and low-power processors.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

prof. Ing. Václav Dvořák, DrSc.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Overview of processor microarchitecture and its future trends, ability to compare processors and using suitable tools, simulate the influence of changes in their architecture. The knowledge of architecture and hardware support of parallel computation on graphic processors can be directly applied for acceleration of intensive calculations. 

Prerequisites

Von Neumann computer architecture, memory hierarchy,   programming in JSI, compiler's tasks and functions

Co-requisites

Not applicable.

Planned learning activities and teaching methods

The course uses teaching methods in form of Lecture - 3 teaching hours per week, Projects - 1 teaching hour per week.

Assesment methods and criteria linked to learning outcomes

To get 20 out of 40 points for projects and midterm examination.

Course curriculum

Syllabus of lectures:
  • Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
  • Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  • Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
  • Optimization of instruction and data fetching. Examples of superscalar CPUs.
  • VLIW processors. SW pipelining, predication, binary translation.
  • Thread-level parallelism. Multithreaded processors, network processors.
  • Data parallelism: vector processors.
  • SIMD ISA extension, GPU and SIMT.
  • Architecture of graphics processing units.
  • Parallel computation on GPU, stream processing, CUDA/OpenCL.
  • Multimedia processors, Cell processor.
  • Signal processors.
  • Low power processors.

Syllabus of numerical exercises:
Tutorials are not scheduled for this course.
Syllabus - others, projects and individual work of students:
  • Superscalar technique of instruction processing (SuperScalar simulator)
  • Performance simulation of memory hierarchy.
  • GPGPU, programming assignment. 

 

Work placements

Not applicable.

Aims

To familiarize students with architecture of the newest processors exploiting the instruction-level and thread-level parallelism. To clarify the role of a compiler and its  cooperation with CPU. To be able to orientate oneself on the processor market, to evaluate and compare various CPUs. Next to familiarize with architecture of graphical processors and its use for acceleration of numerical calculations (GPGPU), with digital signal processors (DSP) and with low-power techniques in processors for mobile applications.  

Specification of controlled education, way of implementation and compensation for absences

Assessment of three small projects, 4 hours each, and a midterm examination.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

  • Baer, J.L.: Microprocessor Architecture. Cambridge University Press, 2010, 367 s., ISBN 978-0-521-76992-1.
  • Hennessy, J.L., Patterson, D.A.: Computer Architecture - A Quantitative Approach. 5. vydání, Morgan Kaufman Publishers, Inc., 2012, 1136 s., ISBN 1-55860-596-7. 
  • Kirk, D., and Hwu, W.: Programming Massively Parallel Processors: A Hands-on Approach, Elsevier, 2010, s. 256, ISBN: 978-0-12-381472-2
  • Jeffers, J., and Reinders, J.: Intel Xeon Phi Coprocessor High Performance Programming, 2013, Morgan Kaufmann, p. 432), ISBN: 978-0-124-10414-3

Recommended reading


Classification of course in study plans

  • Programme IT-MGR-2 Master's

    branch MBI , any year of study, winter semester, elective
    branch MSK , any year of study, winter semester, elective
    branch MIS , any year of study, winter semester, elective
    branch MBS , any year of study, winter semester, compulsory-optional
    branch MIN , any year of study, winter semester, elective
    branch MMI , any year of study, winter semester, compulsory-optional
    branch MMM , any year of study, winter semester, elective
    branch MPV , 2. year of study, winter semester, compulsory
    branch MGM , 2. year of study, winter semester, elective

Type of course unit

 

Lecture

39 hours, optionally

Teacher / Lecturer

prof. Ing. Václav Dvořák, DrSc.

Syllabus

  • Scalar processors. Pipelined instruction processing and instruction dependencies. Typical CPU architecture.
  • Compiler-aided pipelined processing. Superscalar CPU. Dynamic instruction scheduling, branch prediction.
  • Advanced superscalar processing techniques: register renaming, data flow through memory hierarchy.
  • Optimization of instruction and data fetching. Examples of superscalar CPUs.
  • VLIW processors. SW pipelining, predication, binary translation.
  • Thread-level parallelism. Multithreaded processors, network processors.
  • Data paralelism: vector processors.
  • SIMD ISA extension, GPU and SIMT.
  • Architecture of graphics processing units.
  • Parallel computation on GPU, stream processing, CUDA/OpenCL.
  • Multimedia processors, Cell processor.
  • Signal processors.
  • Low power processors.

Project

13 hours, optionally

Teacher / Lecturer

prof. Ing. Václav Dvořák, DrSc.