Course detail

Advanced Digital Systems

FIT-PCSAcad. year: 2010/2011

Not applicable.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

doc. Dr. Ing. Otto Fučík

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Not applicable.

Prerequisites

Not applicable.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Not applicable.

Course curriculum

Not applicable.

Work placements

Not applicable.

Aims

Not applicable.

Specification of controlled education, way of implementation and compensation for absences

Not applicable.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Micheli G., High-Level Synthesis from Algorithm to Digital Circuit, ISBN 978-1-4020-8587-1, 2008 (EN)

Recommended reading

Přednáškové materiály v elektronické podobě.
Rabaey J., Pedram M.: Low Power Design Methodologies, Kluwer, ISBN 0792396308, 1996

Classification of course in study plans

  • Programme IT-MGR-2 Master's

    branch MGM , any year of study, winter semester, compulsory-optional
    branch MSK , any year of study, winter semester, elective
    branch MPS , any year of study, winter semester, elective
    branch MIS , any year of study, winter semester, elective
    branch MBS , any year of study, winter semester, elective
    branch MIN , any year of study, winter semester, elective
    branch MMM , any year of study, winter semester, elective
    branch MMI , 1. year of study, winter semester, compulsory-optional
    branch MBI , 2. year of study, winter semester, compulsory-optional
    branch MPV , 2. year of study, winter semester, compulsory

Type of course unit

 

Lecture

26 hours, optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík

Syllabus

  • Combinational and sequential logic design techniques, algorithms, and tools review.
  • Structured design concept. Design strategies. Design decomposition. Design tools.
  • Introduction to VHDL
  • Basic features of VHDL. Simulation and synthesis.
  • Basic VHDL modeling techniques.
  • Algorithmic level design.
  • Register Level Design.
  • HDL-based design techniques. Constrained design.
  • ASIC and PLD design process. Fast prototyping.
  • Modeling for synthesis.
  • Top-down design methodology in VHDL.
  • Design case study.
  • Design automation algorithms. HW/SW co-design.

Exercise in computer lab

10 hours, optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík

Syllabus

  • Design, schematic diagram drawing, and simulation of a 4-bit full ripple-carry adder.
  • Combinational logic circuits modeling and simulation using VHDL.
  • Sequential logic circuits modeling and simulation using VHDL.
  • A 16-bit, in VHDL described, sequential multiplier modeling, simulation, and implementation.

Project

16 hours, optionally

Teacher / Lecturer

doc. Dr. Ing. Otto Fučík