Course detail

Design of Computer Systems

FIT-INPAcad. year: 2010/2011

Principles of a processor. Introduction to VHDL. Von Neumann computer.  Data types, formats and coding. Instructions, formats, coding and addressing, ISA. VHDL models of algorithms and subsystems. Pipelining. Arithmetic and logic operations. Algorithms and function units. Sequencer: basic function, hard-wired and microprogram implementation. Memories: types, organization, controlling. Memory hierarchies, virtual memory. Peripheral units, buses and bus control, parallel and serial digital interfaces. Performance evaluation. Reliability of computer systems. Introduction to parallel architectures.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

prof. Ing. Lukáš Sekanina, Ph.D.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Students are able to describe the functionality of operation, memory and control units and their communication using VHDL.

The opinion on development trends and possibilities of computer technology.

Prerequisites

Boolean algebra, basics of electrical circuits, basic computer elements, design of combinatorial and sequential circuits.

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

For receiving the credit and thus for entering the exam, students have to get at least 20 points during the semester.

Plagiarism and not allowed cooperation will cause that involved students are not classified and disciplinary action can be initiated.

Course curriculum

  • Introduction, processor and its function.
  • Data representation, accuracy and errors.  
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipelined processing.
  • Algorithms of fixed point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controller.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.

Work placements

Not applicable.

Aims

To give the students the knowledge of organization and functioning of operation, memory and control units, the algorithms with fixed and floating point operations, the way of controlling them and subsystem communication level.

Specification of controlled education, way of implementation and compensation for absences

Within this course, attadance on the lectures and demonstrations is not monitored. The knowledge of students is examined by the projects, the mid-term exam and by the final exam. The minimal number of points which can be obtained from the final exam is 23. Otherwise, no points will be assigned to a student.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Basic literature

Drábek V.: Výstavba počítačů, skripta VUT v Brně, PC-DIR, Brno, 1995. (CS)
Hennessy J. L., Patterson D. A.: Computer Architecture: A Quantitative Approach, 2nd edition, Morgan Kaufmann Publ., 1996, and new editions, e.g. the 5th ed. from 2012.

Recommended reading

Pinker J., Poupa M.: Číslicové systémy a jazyk VHDL, BEN - technická literatura, Praha, 2006. (CS)

Classification of course in study plans

  • Programme IT-BC-3 Bachelor's

    branch BIT , 2. year of study, winter semester, compulsory

Type of course unit

 

Lecture

39 hours, optionally

Teacher / Lecturer

prof. Ing. Lukáš Sekanina, Ph.D.

Syllabus

  • Introduction, processor and its function.
  • Data representation, accuracy and errors.  
  • Instruction sets, register structures.
  • Modelling in VHDL.
  • Pipelined processing.
  • Algorithms of fixed point operations.
  • Algorithms of floating point operations, iterative algorithms.
  • Controller.
  • Memories, cache memory.
  • Buses, peripheral interfacing and control.
  • Computer performance and performance evaluation.
  • Reliability of computer systems.
  • Introduction to parallel architectures.

Fundamentals seminar

6 hours, optionally

Teacher / Lecturer

prof. Ing. Lukáš Sekanina, Ph.D.

Syllabus

  • VHDL
  • Processor in VHDL
  • Huffman code, Hamming code, modular arithmetics 
  • Adders and multipliers
  • Division
  • Iterative algorithms
  • Pipelined processing
  • Performance evaluation, reliability

Project

7 hours, optionally

Teacher / Lecturer

prof. Ing. Lukáš Sekanina, Ph.D.