Publication detail

Self-test RSD A/D COnverter

VEČEŘA, I., VRBA, R.

Original Title

Self-test RSD A/D COnverter

English Title

Self-test RSD A/D COnverter

Type

conference paper

Language

en

Original Abstract

Current mode enables ADC operation down to 3V suitable for battery powered applications. Pipelined SC ADC is designed in 0.6um BiCMOS. Modified redundant-sign-digit conventional-restoring algorithm is implemented. The system integrates band-gap reference and independent supervisory circuit witn 1%accuracy. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Large fault coverage can be reached if creating proper design-for-test. ADC is prepared to meet 1451.2 specifications. The developed models were utilized and SPICE simulations performed.

English abstract

Current mode enables ADC operation down to 3V suitable for battery powered applications. Pipelined SC ADC is designed in 0.6um BiCMOS. Modified redundant-sign-digit conventional-restoring algorithm is implemented. The system integrates band-gap reference and independent supervisory circuit witn 1%accuracy. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Large fault coverage can be reached if creating proper design-for-test. ADC is prepared to meet 1451.2 specifications. The developed models were utilized and SPICE simulations performed.

Keywords

current mode, A/D converter, redundant-sign-digit, test

RIV year

2002

Released

01.01.2002

Publisher

Vysoké učení technické v Brně

Location

Brno

ISBN

80-214-2180-0

Book

ELECTRONIC DEVICES AND SYSTEMS 02 - PROCEEDINGS

Pages from

250

Pages to

254

Pages count

5

Documents

BibTex


@inproceedings{BUT4956,
  author="Ivo {Večeřa} and Radimír {Vrba}",
  title="Self-test RSD A/D COnverter",
  annote="Current mode enables ADC operation down to 3V suitable for battery powered applications. Pipelined SC ADC is designed in 0.6um BiCMOS. Modified redundant-sign-digit conventional-restoring algorithm is implemented. The system integrates band-gap reference and independent supervisory circuit witn 1%accuracy. By changing from pipeline conversion to cycling mode, less power dissipation is obtained at the expense of conversion time. Large fault coverage can be reached if creating proper design-for-test. ADC is prepared to meet 1451.2 specifications. The developed models were utilized and SPICE simulations performed.",
  address="Vysoké učení technické v Brně",
  booktitle="ELECTRONIC DEVICES AND SYSTEMS 02 - PROCEEDINGS",
  chapter="4956",
  institution="Vysoké učení technické v Brně",
  year="2002",
  month="january",
  pages="250",
  publisher="Vysoké učení technické v Brně",
  type="conference paper"
}