Publication detail

Low Power SC Pipelined ADC Using Op-Amp Sharing Approach

HÁZE, J. VRBA, R. SKOČDOPOLE, M. FUJCIK, L.

Original Title

Low Power SC Pipelined ADC Using Op-Amp Sharing Approach

English Title

Low Power SC Pipelined ADC Using Op-Amp Sharing Approach

Type

journal article - other

Language

en

Original Abstract

The paper describes a case study of new 12-bit low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioural modelling regarding low power consumption. It is reached by Op-Amp sharing technique utilisation. The basic block topology design is outlined too. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of Op-Amp etc. are utilized in the design.

English abstract

The paper describes a case study of new 12-bit low power switched-capacitor (SC) ADC for portable applications. The paper is focused on block design of ADC and its behavioural modelling regarding low power consumption. It is reached by Op-Amp sharing technique utilisation. The basic block topology design is outlined too. The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of Op-Amp etc. are utilized in the design.

Keywords

Pipelined ADC, switched-capacitor technique, portable application

RIV year

2004

Released

01.01.2004

Publisher

WSEAS

Location

Rio de Janeiro

Pages from

1959

Pages to

1961

Pages count

3

BibTex 


@article{BUT42219,
  author="Jiří {Háze} and Radimír {Vrba} and Michal {Skočdopole} and Lukáš {Fujcik}",
  title="Low Power SC Pipelined ADC Using Op-Amp Sharing Approach",
  annote="The paper describes a case study of new 12-bit low power switched-capacitor (SC) ADC for portable
applications. The paper is focused on block design of ADC and its behavioural modelling regarding low power
consumption. It is reached by Op-Amp sharing technique utilisation. The basic block topology design is outlined too.
The cancellation techniques for avoiding of capacitor mismatch, clock feedthrough, finite gain and offset of Op-Amp
etc. are utilized in the design.",
  address="WSEAS",
  chapter="42219",
  institution="WSEAS",
  journal="WSEAS Transactions on Circuits",
  number="9",
  volume="2004",
  year="2004",
  month="january",
  pages="1959",
  publisher="WSEAS",
  type="journal article - other"
}