Publication detail

Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints

KŘOUSTEK, J. ŽIDEK, S. KOLÁŘ, D. MEDUNA, A.

Original Title

Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints

English Title

Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints

Type

conference paper

Language

en

Original Abstract

More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.

English abstract

More and more nowadays data processing System-on-Chip (SoC) devices exploit the very long instruction word (VLIW) technology. The high performance of VLIW processors is achieved by a high instruction level parallelism. Program execution is scheduled statically at compilation time. Therefore, there is no need for run-time control mechanisms and hardware can be relatively simple. On the other hand, all constraints checks must be done by the compiler. This paper describes formal method for modeling instruction level limitations of these processors. This method is based on scattered context grammars that generate proper assembler code. This concept has two advantages - formal description of the dependency checking process and high reduction of description complexity over other methods.

Keywords

scattered context grammar, SCG, VLIW, assembler, conflicts, latency

RIV year

2010

Released

11.06.2010

Publisher

Institute of Electrical and Electronics Engineers

Location

Tallinn

ISBN

978-1-4244-7357-1

Book

Proceedings of the 12th Biennial Baltic Electronics Conference

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

165

Pages to

168

Pages count

4

URL

Documents

BibTex


@inproceedings{BUT34822,
  author="Jakub {Křoustek} and Stanislav {Židek} and Dušan {Kolář} and Alexandr {Meduna}",
  title="Exploitation of Scattered Context Grammars to Model VLIW Instruction Constraints",
  annote="More and more nowadays data processing System-on-Chip (SoC) devices exploit the
very long instruction word (VLIW) technology. The high performance of VLIW
processors is achieved by a high instruction level parallelism. Program execution
is scheduled statically at compilation time. Therefore, there is no need for
run-time control mechanisms and hardware can be relatively simple. On the other
hand, all constraints checks must be done by the compiler.

This paper describes formal method for modeling instruction level limitations of
these processors. This method is based on scattered context grammars that
generate proper assembler code. This concept has two advantages - formal
description of the dependency checking process and high reduction of description
complexity over other methods.",
  address="Institute of Electrical and Electronics Engineers",
  booktitle="Proceedings of the 12th Biennial Baltic Electronics Conference",
  chapter="34822",
  doi="10.1109/BEC.2010.5630284",
  edition="NEUVEDEN",
  howpublished="print",
  institution="Institute of Electrical and Electronics Engineers",
  year="2010",
  month="june",
  pages="165--168",
  publisher="Institute of Electrical and Electronics Engineers",
  type="conference paper"
}