On the Efficiency and Security of Quantum-resistant Key Establishment Mechanisms on FPGA Platforms

conference paper

English

The importance of designing efficient and secure post-quantum cryptographic algorithms is reinforced in the recent National Institute of Standards and Technology (NIST)’s Post-Quantum Cryptography (PQC) competitions. Seeking to complement existing studies that evaluate the performance of various PQC algorithms, we explore current hardware implementations of third-round finalist key-establishment algorithms (i.e., Kyber, McEliece, NTRU, and SABER) and the five alternate algorithms (i.e., BIKE, FrodoKEM, HQC, NTRU Prime, and SIKE) on Field Programmable Gate Array (FPGA) platforms. Further, we present our pure-VHDL implementation of Kyber and compare it with the hardware implementations of the NIST finalists. Our design offers one universal Kyber component that can operate in 6 different modes. The evaluation findings show that our pure-VHDL Kyber provides less latency than current VHDL-based implementations.

FPGA; Hardware Implementation; Key Establishment; Post-quantum Cryptography; Security; VHDL

MALINA, L.; RICCI, S.; DOBIÁŠ, P.; JEDLIČKA, P.; HAJNÝ, J.; CHOO, K.

11. 7. 2022

978-989-758-590-6

19th International Conference on Security and Cryptography (SECRYPT 2022)

605

613

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