Publication detail

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination

PODIVÍNSKÝ, J. ČEKAN, O. KRČMA, M. BURGET, R. HRUŠKA, T. KOTÁSEK, Z.

Original Title

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination

English Title

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination

Type

conference paper

Language

en

Original Abstract

A processor forms the basis of almost most of today's electronic devices. In embedded systems, the emphasis is put not only on high performance but also on the small size and low power consumption. Application-specific instruction set processors present a solution that may be optimized for specific applications by different modifications of their parameters where the trade-offs among the parameters may be represented by a Pareto frontier. In this paper, we propose a novel method of Pareto frontier merging to allow the optimization of a processor for a whole set of applications rather than a single one. We provide an experimental evaluation of the method on a model of a RISC-V processor and we show that the proposed method provides better approximation of the source Pareto frontiers than the state-of-the-art methods.

English abstract

A processor forms the basis of almost most of today's electronic devices. In embedded systems, the emphasis is put not only on high performance but also on the small size and low power consumption. Application-specific instruction set processors present a solution that may be optimized for specific applications by different modifications of their parameters where the trade-offs among the parameters may be represented by a Pareto frontier. In this paper, we propose a novel method of Pareto frontier merging to allow the optimization of a processor for a whole set of applications rather than a single one. We provide an experimental evaluation of the method on a model of a RISC-V processor and we show that the proposed method provides better approximation of the source Pareto frontiers than the state-of-the-art methods.

Keywords

Pareto frontier, processor optimization, ASIP

Released

25.02.2020

Publisher

IEEE Circuits and Systems Society

Location

San José

ISBN

978-1-7281-3427-7

Book

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

1

Pages to

4

Pages count

4

URL

Documents

BibTex


@inproceedings{BUT162659,
  author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination",
  annote="A processor forms the basis of almost most of today's electronic devices. In
embedded systems, the emphasis is put not only on high performance but also on
the small size and low power consumption. Application-specific instruction set
processors present a solution that may be optimized for specific applications by
different modifications of their parameters where the trade-offs among the
parameters may be represented by a Pareto frontier. In this paper, we propose
a novel method of Pareto frontier merging to allow the optimization of
a processor for a whole set of applications rather than a single one. We provide
an experimental evaluation of the method on a model of a RISC-V processor and we
show that the proposed method provides better approximation of the source Pareto
frontiers than the state-of-the-art methods.",
  address="IEEE Circuits and Systems Society",
  booktitle="2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)",
  chapter="162659",
  doi="10.1109/LASCAS45839.2020.9068954",
  edition="NEUVEDEN",
  howpublished="online",
  institution="IEEE Circuits and Systems Society",
  year="2020",
  month="february",
  pages="1--4",
  publisher="IEEE Circuits and Systems Society",
  type="conference paper"
}