Publication detail

FPGA Implementation of Multiplierless Low-Pass FIR Differentiator

SOVA, V. BRABLC, M. GREPL, R.

Original Title

FPGA Implementation of Multiplierless Low-Pass FIR Differentiator

English Title

FPGA Implementation of Multiplierless Low-Pass FIR Differentiator

Type

conference paper

Language

en

Original Abstract

In this paper we present, that if we appropriately choose the parameters of the maximally flat FIR differentiator, the coefficients of the filter will have a common divisor which is reciprocal to a power of two. That means that the entire filter can be implemented in a very cost-effective way using only shift and add operations, which is beneficial mainly when the filter is implemented on the FPGA. Proposed differentiator was implemented on an FPGA and tested in real time. At the end of the article we compare the FPGA resource utilization for the proposed maximally-flat FIR differentiator and a differentiator designed using a common approach.

English abstract

In this paper we present, that if we appropriately choose the parameters of the maximally flat FIR differentiator, the coefficients of the filter will have a common divisor which is reciprocal to a power of two. That means that the entire filter can be implemented in a very cost-effective way using only shift and add operations, which is beneficial mainly when the filter is implemented on the FPGA. Proposed differentiator was implemented on an FPGA and tested in real time. At the end of the article we compare the FPGA resource utilization for the proposed maximally-flat FIR differentiator and a differentiator designed using a common approach.

Keywords

differentiator, FPGA, multiplierless, FIR

Released

23.01.2019

ISBN

978-80-214-5542-9

Book

PROCEEDINGS OF THE 2018 18TH INTERNATIONAL CONFERENCE ON MECHATRONICS - MECHATRONIKA (ME)

Pages from

382

Pages to

386

Pages count

5

Documents

BibTex


@inproceedings{BUT152524,
  author="Václav {Sova} and Martin {Brablc} and Robert {Grepl}",
  title="FPGA Implementation of Multiplierless Low-Pass FIR Differentiator",
  annote="In this paper we present, that if we appropriately choose the parameters of the maximally flat FIR differentiator,
the coefficients of the filter will have a common divisor which is reciprocal to a power of two. That means that the entire filter can be implemented in a very cost-effective way using only shift and add operations, which is beneficial mainly when the filter is implemented on the FPGA. Proposed differentiator was implemented on an FPGA and tested in real time. At the end of the article we compare the FPGA resource utilization for the
proposed maximally-flat FIR differentiator and a differentiator designed using a common approach.",
  booktitle="PROCEEDINGS OF THE 2018 18TH INTERNATIONAL CONFERENCE ON MECHATRONICS - MECHATRONIKA (ME)",
  chapter="152524",
  howpublished="online",
  year="2019",
  month="january",
  pages="382--386",
  type="conference paper"
}