Publication detail

Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement

Lukas Fujcik, Radimir Vrba, Thibault Mougel, Anna Kuncheva

Original Title

Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement

English Title

Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement

Type

conference paper

Language

en

Original Abstract

This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages).

English abstract

This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages).

Keywords

Modeling, Design, Novel Architecture, Sigma-Delta Converter, Sensor Measurement

RIV year

2005

Released

01.01.2005

Publisher

Ing. Zdenek Novotny CSc.

Location

Brno

ISBN

80-214-2990-9

Book

EDS'05 IMAPS CS INTERNATIONAL CONFERENCE PROCEEDINGS

Pages from

148

Pages to

153

Pages count

6

Documents

BibTex


@inproceedings{BUT15244,
  author="Lukáš {Fujcik} and Radimír {Vrba} and Thibault {Mougel}",
  title="Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement",
  annote="This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages).",
  address="Ing. Zdenek Novotny CSc.",
  booktitle="EDS'05 IMAPS CS INTERNATIONAL CONFERENCE PROCEEDINGS",
  chapter="15244",
  institution="Ing. Zdenek Novotny CSc.",
  year="2005",
  month="january",
  pages="148",
  publisher="Ing. Zdenek Novotny CSc.",
  type="conference paper"
}