Publication detail

Advanced Mapping Techniques for Digital Signal Processors

FRÝZA, T. MEGO, R.

Original Title

Advanced Mapping Techniques for Digital Signal Processors

English Title

Advanced Mapping Techniques for Digital Signal Processors

Type

conference paper

Language

en

Original Abstract

This paper is focused on the hardware modeling and mapping the algorithms on the many-, multi -core platforms, such as TMS320C6678 digital signal processor (DSP) with the very long instruction word (VLIW) architecture. The main methods to develop an application for the target processor combine high- and/or low-level programming languages. Although the hardware capabilities of the nowadays processors and compilers are persistently increasing, the programmers common practice is to hand-optimize critical parts of the digital signal processing algorithms in assembly code. In the paper the benefit of the auxiliary tool for generating of semi-optimal codes for the DSP is presented. The functions for basic vector operations (addition, multiplication, and dot product) were proposed by this tool and the computing performances were compared to the corresponding functions from the TMS320C6000 DSP Library (DSPLIB). Comparing the functions' duration, the proposed routines achieve the average acceleration of 24 CPU cycles.

English abstract

This paper is focused on the hardware modeling and mapping the algorithms on the many-, multi -core platforms, such as TMS320C6678 digital signal processor (DSP) with the very long instruction word (VLIW) architecture. The main methods to develop an application for the target processor combine high- and/or low-level programming languages. Although the hardware capabilities of the nowadays processors and compilers are persistently increasing, the programmers common practice is to hand-optimize critical parts of the digital signal processing algorithms in assembly code. In the paper the benefit of the auxiliary tool for generating of semi-optimal codes for the DSP is presented. The functions for basic vector operations (addition, multiplication, and dot product) were proposed by this tool and the computing performances were compared to the corresponding functions from the TMS320C6000 DSP Library (DSPLIB). Comparing the functions' duration, the proposed routines achieve the average acceleration of 24 CPU cycles.

Keywords

VLIW;DSP;algorithm mapping;manycore;multicore;TMS320C6678;vector operations

Released

14.12.2016

Publisher

IEEE

Location

Cyprus

ISBN

978-1-5090-2902-0

Book

16th IEEE International Symposium on Signal Processing and Information Technology

Pages from

1

Pages to

4

Pages count

4

BibTex


@inproceedings{BUT129540,
  author="Tomáš {Frýza} and Roman {Mego}",
  title="Advanced Mapping Techniques for Digital Signal Processors",
  annote="This paper is focused on the hardware modeling and mapping the algorithms on the many-, multi -core platforms, such as TMS320C6678 digital signal processor (DSP) with the very long instruction word (VLIW) architecture. The main methods to develop an application for the target processor combine high- and/or low-level programming languages. Although the hardware capabilities of the nowadays processors and compilers are persistently increasing, the programmers common practice is to hand-optimize critical parts of the digital signal processing algorithms in assembly code. In the paper the benefit of the auxiliary tool for generating of semi-optimal codes for the DSP is presented. The functions for basic vector operations (addition, multiplication, and dot product) were proposed by this tool and the computing performances were compared to the corresponding functions from the TMS320C6000 DSP Library (DSPLIB). Comparing the functions' duration, the proposed routines achieve the average acceleration of 24 CPU cycles.
",
  address="IEEE",
  booktitle="16th IEEE International Symposium on Signal Processing and Information Technology",
  chapter="129540",
  doi="10.1109/ICCES.2018.8639186",
  howpublished="online",
  institution="IEEE",
  year="2016",
  month="december",
  pages="1--4",
  publisher="IEEE",
  type="conference paper"
}