Publication detail

Frequency Domain FIR Filter Optimization for Multi-core C6678 DSP

FRÝZA, T. MEGO, R.

Original Title

Frequency Domain FIR Filter Optimization for Multi-core C6678 DSP

Type

conference paper

Language

English

Original Abstract

This paper is focused on the optimal utilization of hardware resources within a processor during the execution of desired source codes. As an example, the algorithm which is commonly used for performance benchmarks was applied. In this paper we optimize the signal processing algorithm, FDFIR (Frequency Domain FIR filter) for the specific architecture of the eight-core digital signal processor TMS320C6678. This algorithm is suitable for benchmarking because it contains both forward and inverse Fast Fourier Transform and vector multiplication as well. The goal of the analysis is to describe and avoid any idle operations in the algorithm which extend the computational time and increase the power consumption of the processor. The proposed approaches were explained in detail for a test case with a very short vector length.

Keywords

FDFIR, optimization, implementation, C6678, DSP

Authors

FRÝZA, T.; MEGO, R.

Released

26. 4. 2016

Publisher

IEEE

Location

Žilina, Slovensko

ISBN

978-1-5090-1674-7

Book

26th International Conference Radioelektronika

Pages from

1

Pages to

4

Pages count

4

URL

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7477430

BibTex

@inproceedings{BUT127011,
  author="Tomáš {Frýza} and Roman {Mego}",
  title="Frequency Domain FIR Filter Optimization for Multi-core C6678 DSP",
  booktitle="26th International Conference Radioelektronika",
  year="2016",
  pages="1--4",
  publisher="IEEE",
  address="Žilina, Slovensko",
  doi="10.1109/RADIOELEK.2016.7477430",
  isbn="978-1-5090-1674-7",
  url="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7477430"
}