Publication detail

Instructor Selector Generation from Architecture Description

TRMAČ, M. HUSÁR, A. HRANÁČ, J. HRUŠKA, T. MASAŘÍK, K.

Original Title

Instructor Selector Generation from Architecture Description

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level.

The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized
pseudo-registers and special cases of immediate operands.

Keywords

compiler, instruction selection, LLVM, ISAC

Authors

TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K.

RIV year

2010

Released

24. 11. 2010

Publisher

Masaryk University

Location

Brno

ISBN

978-80-87342-10-7

Book

6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

167

Pages to

174

Pages count

8

BibTex

@inproceedings{BUT37045,
  author="Miloslav {Trmač} and Adam {Husár} and Jan {Hranáč} and Tomáš {Hruška} and Karel {Masařík}",
  title="Instructor Selector Generation from Architecture Description",
  booktitle="6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2010",
  pages="167--174",
  publisher="Masaryk University",
  address="Brno",
  isbn="978-80-87342-10-7"
}