Publication detail

Power Conscious RTL Test Scheduling

ŠKARVADA, J. KOTÁSEK, Z. HERRMAN, T.

Original Title

Power Conscious RTL Test Scheduling

English Title

Power Conscious RTL Test Scheduling

Type

conference paper

Language

en

Original Abstract

In the paper, a methodology of power conscious RTL test scheduling is described. The methodology is based on the fact that circuit under analysis (CUA) is partitioned into testable blocks (TB), the information about the partitioning is the input information for the methodology. TBs are mapped into AMI platform, for each TB the sequences of test vectors are then derived, a professional tool is used for this purpose. The sequences of test vectors are then reordered with the goal to reduce power consumption during test application by reducing switching activities. The power consumption estimation is combined with the implemented platform which allows to gain more precise results. The values of TBs power consumption are then used in RTL test scheduling methodology. The goal is to find test schedule with lowest test application time and lower power consumption than the required maximal value.

English abstract

In the paper, a methodology of power conscious RTL test scheduling is described. The methodology is based on the fact that circuit under analysis (CUA) is partitioned into testable blocks (TB), the information about the partitioning is the input information for the methodology. TBs are mapped into AMI platform, for each TB the sequences of test vectors are then derived, a professional tool is used for this purpose. The sequences of test vectors are then reordered with the goal to reduce power consumption during test application by reducing switching activities. The power consumption estimation is combined with the implemented platform which allows to gain more precise results. The values of TBs power consumption are then used in RTL test scheduling methodology. The goal is to find test schedule with lowest test application time and lower power consumption than the required maximal value.

Keywords

Test scheduling, testable block, power consumption, test vectors reordering, integer linear programming

RIV year

2008

Released

02.06.2008

Publisher

IEEE Computer Society

Location

Los Alamitos

ISBN

978-0-7695-3277-6

Book

Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

721

Pages to

728

Pages count

8

URL

BibTex


@inproceedings{BUT30497,
  author="Jaroslav {Škarvada} and Zdeněk {Kotásek} and Tomáš {Herrman}",
  title="Power Conscious RTL Test Scheduling",
  annote="In the paper, a methodology of power conscious RTL test
scheduling is described. The methodology is based on the
fact that circuit under analysis (CUA) is partitioned into
testable blocks (TB), the information about the partitioning
is the input information for the methodology. TBs are
mapped into AMI platform, for each TB the sequences of
test vectors are then derived, a professional tool is used
for this purpose. The sequences of test vectors are then reordered
with the goal to reduce power consumption during
test application by reducing switching activities. The power
consumption estimation is combined with the implemented
platform which allows to gain more precise results. The
values of TBs power consumption are then used in RTL test
scheduling methodology. The goal is to find test schedule
with lowest test application time and lower power consumption
than the required maximal value.",
  address="IEEE Computer Society",
  booktitle="Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools",
  chapter="30497",
  edition="NEUVEDEN",
  howpublished="print",
  institution="IEEE Computer Society",
  year="2008",
  month="june",
  pages="721--728",
  publisher="IEEE Computer Society",
  type="conference paper"
}