Publication detail

Speeding-up OAS and AAS Communication in Networking System on Chips

JAROŠ, J., DVOŘÁK, V.

Original Title

Speeding-up OAS and AAS Communication in Networking System on Chips

English Title

Speeding-up OAS and AAS Communication in Networking System on Chips

Type

conference paper

Language

en

Original Abstract

As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.

English abstract

As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.

Keywords

BOA algorithm, communication patterns, multiprocessor topology, hypercube, AMP

RIV year

2005

Released

21.04.2005

Publisher

University of West Hungary

Location

Sopron

ISBN

9639364487

Book

Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems

Pages from

206

Pages to

209

Pages count

4

BibTex


@inproceedings{BUT21469,
  author="Jiří {Jaroš} and Václav {Dvořák}",
  title="Speeding-up OAS and AAS Communication in Networking System on Chips",
  annote="As chip multiprocessors are quickly penetrating new application areas in network and media processing, their interconnection architectures become a subject of optimization. Group communications are frequently used in many parallel algorithms and if their overhead is excessive, performance degrades rapidly with processor count. This paper deals with the design of a new application specific Bayesian Optimization Algorithm (BOA) and Standard Genetic Algorithm (SGA) that both produce almost optimal communication schedules for an arbitrary multiprocessor topology. We demonstrated the optimization process on hypercube and AMP topology using WH (Wormhole) switching.",
  address="University of West Hungary",
  booktitle="Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems",
  chapter="21469",
  institution="University of West Hungary",
  year="2005",
  month="april",
  pages="206",
  publisher="University of West Hungary",
  type="conference paper"
}