Publication detail

On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

JEDLIČKA, P. MALINA, L. SOCHA, P. GERLICH, T. MARTINÁSEK, Z. HAJNÝ, J.

Original Title

On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

Type

conference paper

Language

English

Original Abstract

Currently, many post-quantum cryptography schemes have been implemented on various hardware platforms in order to provide efficient solutions in cybersecurity services. As researchers and hardware developers focus primarily on designs providing small latency and requiring fewer hardware resources, their implementations could seldom omit protection techniques against various physical attacks. This paper studies potential attacks on the cryptography implementations that run on Field-Programmable Gate Array (FPGA) platforms. We mainly analyze how Post-Quantum Cryptography (PQC) implementations could be vulnerable on various platforms. Further, we aim at the FPGA-based implementations of National Institute of Standards and Technology (NIST)’s PQC competition finalists. Our study should present to developers the current overview of attacks and countermeasures that can be implemented on specific PQC schemes on FPGA platforms. Moreover, we present novel implementation of one universal countermeasure component and reveal additional resources that are needed.

Keywords

Applied Cryptography; FPGA; Hardware Implementation; Post-Quantum Cryptography; Secure Implementation; Side Channel Attacks

Authors

JEDLIČKA, P.; MALINA, L.; SOCHA, P.; GERLICH, T.; MARTINÁSEK, Z.; HAJNÝ, J.

Released

23. 8. 2022

Publisher

ACM

Location

Vienna, Austria

ISBN

978-1-4503-9670-7

Book

ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security

Pages from

1

Pages to

9

Pages count

9

URL

https://dl.acm.org/doi/abs/10.1145/3538969.3544423

BibTex

@inproceedings{BUT178902,
  author="Petr {Jedlička} and Lukáš {Malina} and Petr {Socha} and Tomáš {Gerlich} and Zdeněk {Martinásek} and Jan {Hajný}",
  title="On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography",
  booktitle="ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security",
  year="2022",
  pages="1--9",
  publisher="ACM",
  address="Vienna, Austria",
  doi="10.1145/3538969.3544423",
  isbn="978-1-4503-9670-7",
  url="https://dl.acm.org/doi/abs/10.1145/3538969.3544423"
}