Publication detail

Formal Specifications of an Extended Phase-Parallel Model of Stream Processing

DVOŘÁK, V.

Original Title

Formal Specifications of an Extended Phase-Parallel Model of Stream Processing

English Title

Formal Specifications of an Extended Phase-Parallel Model of Stream Processing

Type

conference paper

Language

en

Original Abstract

Partitioning of computationally expensive problems among tens of processors is becoming a real-life problem in systems on a chip embedded in consumer electronics. With chips capable of (partial) reconfiguration, this task is by no means trivial. The paper addresses this problem by suggesting high-level formal specifications (FS) of parallel reconfigurable computation. Being executable, they could be used mainly for fast performance tuning without an underlying hardware prototype. The FS proposal extends the less known Phase-Parallel Model of parallel computing.

English abstract

Partitioning of computationally expensive problems among tens of processors is becoming a real-life problem in systems on a chip embedded in consumer electronics. With chips capable of (partial) reconfiguration, this task is by no means trivial. The paper addresses this problem by suggesting high-level formal specifications (FS) of parallel reconfigurable computation. Being executable, they could be used mainly for fast performance tuning without an underlying hardware prototype. The FS proposal extends the less known Phase-Parallel Model of parallel computing.

Keywords

Group communications, Reconfigurable parallel processing, Phase Parallel Model, Performance prediction

RIV year

2004

Released

21.05.2004

Publisher

University of Stirling

Location

Stirling

ISBN

1-85769-1970

Book

Proc. of Joint Workshop on Formal Specifications of Computer-Based Systems

Pages from

37

Pages to

44

Pages count

8

BibTex


@inproceedings{BUT17120,
  author="Václav {Dvořák}",
  title="Formal Specifications of an Extended Phase-Parallel Model of Stream Processing",
  annote="Partitioning of computationally expensive problems among tens of processors is becoming a real-life problem in systems on a chip embedded in consumer electronics. With chips capable of (partial) reconfiguration, this task is by no means trivial. The paper addresses this problem by suggesting high-level formal specifications (FS) of parallel reconfigurable computation. Being executable, they could be used mainly for fast performance tuning without an underlying hardware prototype. The FS proposal extends the less known Phase-Parallel Model of parallel computing.",
  address="University of Stirling",
  booktitle="Proc. of Joint Workshop on Formal Specifications of Computer-Based Systems",
  chapter="17120",
  institution="University of Stirling",
  year="2004",
  month="may",
  pages="37--44",
  publisher="University of Stirling",
  type="conference paper"
}