Publication detail

High-speed Regular Expression Matching with Pipelined Memory-based Automata

MATOUŠEK, D. MATOUŠEK, J. KOŘENEK, J.

Original Title

High-speed Regular Expression Matching with Pipelined Memory-based Automata

Type

abstract

Language

English

Original Abstract

The paper proposes an architecture of a high-speed regular expression (RE) matching system with fast updates of an RE set. The architecture uses highly memory-efficient Delayed Input DFAs (D 2 FAs), which are organized to a processing pipeline. The architecture is designed so that it communicates only locally among its components in order to achieve high frequency even for a large number of parallel matching engines (MEs), which allows scaling throughput to hundreds of gigabits per second (Gbps). The architecture is able to achieve processing throughput of up to 400 Gbps on current FPGA chips.

Keywords

Regular expression matching, 100 Gbps, 400 Gbps, Delayed Input DFA, Pipelined automata

Authors

MATOUŠEK, D.; MATOUŠEK, J.; KOŘENEK, J.

Released

7. 9. 2018

Publisher

IEEE Computer Society

Location

Boulder, CO

ISBN

978-1-5386-5522-1

Book

Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018

Pages from

214

Pages to

214

Pages count

1

URL

https://ieeexplore.ieee.org/document/8457663

BibTex

@misc{BUT163346,
  author="Denis {Matoušek} and Jiří {Matoušek} and Jan {Kořenek}",
  title="High-speed Regular Expression Matching with Pipelined Memory-based Automata",
  booktitle="Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018",
  year="2018",
  pages="214--214",
  publisher="IEEE Computer Society",
  address="Boulder, CO",
  doi="10.1109/FCCM.2018.00048",
  isbn="978-1-5386-5522-1",
  url="https://ieeexplore.ieee.org/document/8457663",
  note="abstract"
}