Publication detail

Design of decimation filter for novel Sigma-Delta modulator

Lukas Fujcik, Thibault Mougel

Original Title

Design of decimation filter for novel Sigma-Delta modulator

English Title

Design of decimation filter for novel Sigma-Delta modulator

Type

conference paper

Language

en

Original Abstract

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.

English abstract

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.

Keywords

sigma-delta modulator, decimation filter

RIV year

2005

Released

01.01.2005

Publisher

Technical University of Sofia

Location

Bulgaria

ISBN

954-438-521-5

Book

THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005

Pages from

58

Pages to

63

Pages count

6

BibTex


@inproceedings{BUT15924,
  author="Lukáš {Fujcik} and Thibault {Mougel}",
  title="Design of decimation filter for novel Sigma-Delta modulator",
  annote="This paper describes steps involved in a new
VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values.
Finally, by analyzing the design, we can find an
efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 µm technology.",
  address="Technical University of Sofia",
  booktitle="THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005",
  chapter="15924",
  institution="Technical University of Sofia",
  year="2005",
  month="january",
  pages="58",
  publisher="Technical University of Sofia",
  type="conference paper"
}