Packet Classification with Limited Memory Resources

conference paper

English

Network security and monitoring devices use packet classification to match packet header fields in a set of rules. Many hardware architectures have been designed to accelerate packet classification and achieve wire-speed throughput for 100Gbps networks. The architectures are designed for high throughput even for the shortest packets. However, FPGA SoC and Intel Xeon with FPGA have limited resources for multiple accelerators. Usually, it is necessary to balance between available resources and the level of acceleration. Therefore, we have designed new hardware architecture for packet classification, which can balance between the processing speed and hardware resources. To achieve 10 Gbps average throughput the architecture need only 20 BlockRAMs for 5500 rules. Moreover, the architecture can scale the processing speed to wire-speed throughput on 100 Gbps line at the cost of additional memory resources.

DCFL, packet classification, FPGA, P4

KEKELY, M.; KOŘENEK, J.

30. 8. 2017

Institute of Electrical and Electronics Engineers

Vieden

978-1-5386-2145-5

In proceedings 2017 Euromicro Conference on Digital System Design

179

183

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