Publication detail

Zero Cross Detection Using Phase Locked Loop

ŠŤASTNÝ, L. MEGO, R. FRANEK, L. BRADÁČ, Z.

Original Title

Zero Cross Detection Using Phase Locked Loop

English Title

Zero Cross Detection Using Phase Locked Loop

Type

conference paper

Language

en

Original Abstract

This paper discusses zero cross detection method for the time synchronization purpose that is based on phase locked loop. After familiarizing with PLL concept and its blocks, example design of the PLL is realized. Simulation schema is introduced to examine and analyse PLL behaviour under different grid interferences. Performed tests show two potential issues multiple zero crossing in the zero cross area may cause instability of the loop and the presence of harmonics may cause shifts of the zero cross event.

English abstract

This paper discusses zero cross detection method for the time synchronization purpose that is based on phase locked loop. After familiarizing with PLL concept and its blocks, example design of the PLL is realized. Simulation schema is introduced to examine and analyse PLL behaviour under different grid interferences. Performed tests show two potential issues multiple zero crossing in the zero cross area may cause instability of the loop and the presence of harmonics may cause shifts of the zero cross event.

Keywords

zero crossings, detection algorithms, phase-locked loop, grid interferences

Released

05.10.2016

Location

Brno/Lednice

ISBN

2405-8963

Periodical

IFAC-PapersOnLine (ELSEVIER)

Year of study

2016

Number

14

State

NL

Pages from

464

Pages to

468

Pages count

5

Documents

BibTex


@inproceedings{BUT128785,
  author="Ladislav {Šťastný} and Roman {Mego} and Lešek {Franek} and Zdeněk {Bradáč}",
  title="Zero Cross Detection Using Phase Locked Loop",
  annote="This paper discusses zero cross detection method for the time synchronization
purpose that is based on phase locked loop. After familiarizing with PLL concept and its blocks,
example design of the PLL is realized. Simulation schema is introduced to examine and analyse
PLL behaviour under different grid interferences. Performed tests show two potential issues
multiple zero crossing in the zero cross area may cause instability of the loop and the presence
of harmonics may cause shifts of the zero cross event.",
  booktitle="14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016",
  chapter="128785",
  doi="10.1016/j.ifacol.2016.12.050",
  howpublished="electronic, physical medium",
  number="14",
  year="2016",
  month="october",
  pages="464--468",
  type="conference paper"
}